Patents by Inventor Hajime Kimura

Hajime Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230019498
    Abstract: The present invention has a pixel which includes a first switch, a second switch, a third switch, a first resistor, a second resistor, a first liquid crystal element, and a second liquid crystal element. A pixel electrode of the first liquid crystal element is electrically connected to a signal line through the first switch. The pixel electrode of the first liquid crystal element is electrically connected to a pixel electrode of the second liquid crystal element through the second switch and the first resistor. The pixel electrode of the second liquid crystal element is electrically connected to a Cs line through the third switch and the second resistor. A common electrode of the first liquid crystal element is electrically connected to a common electrode of the second liquid crystal element.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Inventor: Hajime Kimura
  • Publication number: 20230014360
    Abstract: To provide an electronic device capable of recognizing a user's emotion with a high accuracy. The electronic device includes a detection device, an arithmetic device, and a housing. The housing includes a space at a position overlapping with a user's nose when the user wears the electronic device. The detection device is located between the housing and the user's nose. The detection device has a function of obtaining user's data on an emotion of the user and outputting the user's data to the arithmetic device. The arithmetic device has a function of generating display data based on the user's data and outputting the display data.
    Type: Application
    Filed: November 30, 2020
    Publication date: January 19, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Rihito WADA
  • Patent number: 11551596
    Abstract: To suppress degradation of a transistor. A method for driving a liquid crystal display device has a first period and a second period. In the first period, a first transistor and a second transistor are alternately turned on and off repeatedly, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are alternately turned on and off repeatedly. Accordingly, the time during which the transistor is on can be reduced, so that degradation of characteristics of the transistor can be suppressed.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: January 10, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Atsushi Umezaki
  • Publication number: 20230005446
    Abstract: A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of onion of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/?m (1×10?18 A/?m) or less. Therefore, the drive capability of the semiconductor device can be improved.
    Type: Application
    Filed: September 13, 2022
    Publication date: January 5, 2023
    Inventors: Atsushi UMEZAKI, Hajime KIMURA
  • Publication number: 20230004051
    Abstract: The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.
    Type: Application
    Filed: September 2, 2022
    Publication date: January 5, 2023
    Inventor: Hajime Kimura
  • Publication number: 20230005443
    Abstract: The resolution of a low-resolution image is made high and a stereoscopic image is displayed. Resolution is made high by super-resolution processing. In this case, the super-resolution processing is performed after edge enhancement processing is performed. Accordingly, a stereoscopic image with high resolution and high quality can be displayed. Alternatively, after image analysis processing is performed, edge enhancement processing and super-resolution processing are concurrently performed. Accordingly, processing time can be shortened.
    Type: Application
    Filed: September 14, 2022
    Publication date: January 5, 2023
    Inventor: Hajime KIMURA
  • Publication number: 20230005518
    Abstract: An object is to shorten the time for rewriting data in memory cells. A memory module includes a first memory cell, a second memory cell, a selection transistor, and a wiring WBL1. The first memory cell includes a first memory node. The second memory cell includes a second memory node. One end of the first memory cell is electrically connected to the wiring WBL1 through the selection transistor. The other end of the first memory cell is electrically connected to one end of the second memory cell. The other end of the second memory cell is electrically connected to the wiring WBL1. When the selection transistor is on, data in the first memory node is rewritten by a signal supplied through the selection transistor to the wiring WBL1. When the selection transistor is off, data in the first memory node is rewritten by a signal supplied through the second memory node to the wiring WBL1.
    Type: Application
    Filed: September 12, 2022
    Publication date: January 5, 2023
    Inventors: Hajime KIMURA, Takahiro FUKUTOME
  • Patent number: 11543700
    Abstract: A low-resolution image is displayed at high resolution and power consumption is reduced. Resolution is made higher by super-resolution processing. Then, display is performed with the luminance of a backlight controlled by local dimming after the super-resolution processing. By controlling the luminance of the backlight, power consumption can be reduced. Further, by performing the local dimming ater the super-resolution processing, accurate display can be performed.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: January 3, 2023
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Hajime Kimura
  • Patent number: 11545578
    Abstract: A semiconductor device with high reliability is provided. The semiconductor device includes a first insulator, a second insulator, and a transistor; the transistor includes an oxide in a channel formation region; the oxide is surrounded by the first insulator; and the first insulator is surrounded by the second insulator. The first insulator includes a region with a lower hydrogen concentration than the second insulator. Alternatively, the first insulator includes a region with a lower hydrogen concentration than the second insulator and with a lower nitrogen concentration than the second insulator.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 3, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasumasa Yamane, Takashi Hirose, Teruyuki Fujii, Hajime Kimura, Daigo Shimada
  • Publication number: 20220414960
    Abstract: An information processing device including a control unit that displays a virtual object on a three-dimensional coordinate space associated with a real space and causes the virtual object to perform a predetermined movement according to a predetermined sound reproduced from a real sound source disposed in the real space, in which the control unit performs delay amount setting processing of increasing a delay amount of movement start timing at which the virtual object is caused to perform the predetermined movement with respect to reproduction timing at which the real sound source reproduces the predetermined sound, as a position of the real sound source in the real space and a position of the virtual object on the three-dimensional coordinate space are separated from each other.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 29, 2022
    Applicant: SONY GROUP CORPORATION
    Inventors: Takaomi KIMURA, Yasuko ISHIHARA, Hajime WAKABAYASHI, Atsushi ISHIHARA, Masayuki INOUE, Hirotake ICHIKAWA, Hidenori AOKI, Ryo FUKAZAWA
  • Publication number: 20220416060
    Abstract: A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.
    Type: Application
    Filed: August 26, 2022
    Publication date: December 29, 2022
    Inventor: Hajime KIMURA
  • Publication number: 20220393035
    Abstract: A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is controlled with a signal held in the capacitor and a signal output from the inverter so that voltage is supplied to the display element. The inverter and the switch can be constituted by transistors with the same polarity. A semiconductor layer included in the pixel may be formed using a light-transmitting material. Moreover, a gate electrode, a drain electrode, and a capacitor electrode may be formed using a light-transmitting conductive layer. The pixel is formed using a light-transmitting material in such a manner, whereby the display device can be a transmissive display device while including a pixel having a memory.
    Type: Application
    Filed: August 12, 2022
    Publication date: December 8, 2022
    Inventors: Hajime KIMURA, Kengo AKIMOTO, Masashi TSUBUKU, Toshinari SASAKI
  • Patent number: 11520185
    Abstract: The present invention has a pixel which includes a first switch, a second switch, a third switch, a first resistor, a second resistor, a first liquid crystal element, and a second liquid crystal element. A pixel electrode of the first liquid crystal element is electrically connected to a signal line through the first switch. The pixel electrode of the first liquid crystal element is electrically connected to a pixel electrode of the second liquid crystal element through the second switch and the first resistor. The pixel electrode of the second liquid crystal element is electrically connected to a Cs line through the third switch and the second resistor. A common electrode of the first liquid crystal element is electrically connected to a common electrode of the second liquid crystal element.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: December 6, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 11520193
    Abstract: An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: December 6, 2022
    Inventors: Hajime Kimura, Shunpei Yamazaki
  • Patent number: 11522105
    Abstract: An object of the present disclosure is to provide a technique capable of attaining an AlN template which has less strain and is suitable for producing the ultraviolet LED. Provided is a nitride semiconductor laminate structure, including at least a sapphire substrate, a first AlN layer formed on a principal surface of the sapphire substrate, and a second AlN layer formed on the first AlN layer, wherein an absolute value of a strain amount ?2 of the second AlN layer in the a-axis direction is smaller than an absolute value of a strain amount ?1 of the first AlN layer in the a-axis direction.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: December 6, 2022
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Taichiro Konno, Takeshi Kimura, Hajime Fujikura
  • Publication number: 20220382085
    Abstract: A pixel electrode or a common electrode is a light-transmissive conductive film; therefore, it is formed of ITO conventionally. Accordingly, the number of manufacturing steps and masks, and manufacturing cost have been increased. An object of the present invention is to provide a semiconductor device, a liquid crystal display device, and an electronic appliance each having a wide viewing angle, less numbers of manufacturing steps and masks, and low manufacturing cost compared with a conventional device. A semiconductor layer of a transistor, a pixel electrode, and a common electrode of a liquid crystal element are formed in the same step.
    Type: Application
    Filed: July 28, 2022
    Publication date: December 1, 2022
    Inventor: Hajime KIMURA
  • Publication number: 20220384536
    Abstract: A display apparatus capable of performing image capturing with high sensitivity is provided. The display apparatus includes a light-emitting element including a light-emitting layer, and a light-receiving element including a photoelectric conversion layer. A transflective electrode is provided over the light-emitting layer, and a transparent electrode is provided over the photoelectric conversion layer. With a structure where the transflective electrode does not overlap the photoelectric conversion layer, a reduction in light-receiving sensitivity of the light-receiving element can be prevented while a microcavity structure is used for the light-emitting element. Thus, the display apparatus can emit light with high color purity and perform image capturing with high sensitivity.
    Type: Application
    Filed: May 12, 2022
    Publication date: December 1, 2022
    Inventors: Hajime KIMURA, Kentaro HAYASHI
  • Publication number: 20220385284
    Abstract: In a semiconductor device capable of product-sum operation, variations in transistor characteristics are reduced. The semiconductor device includes a first circuit including a driver unit, a correction unit, and a holding unit, and an inverter circuit. The first circuit has a function of generating an inverted signal of a signal input to an input terminal of the first circuit and outputting the inverted signal to an output terminal of the first circuit. The driver unit includes a p-channel first transistor and an n-channel second transistor having a back gate. The correction unit has a function of correcting the threshold voltage of one or both of the first transistor and the second transistor. The holding unit has a function of holding the potential of the back gate of the second transistor. The output terminal of the first circuit is electrically connected to an input terminal of the inverter circuit.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hajime KIMURA, Yoshiyuki KUROKAWA, Tatsunori INOUE
  • Publication number: 20220384522
    Abstract: A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Inventors: Hajime KIMURA, Yoshiyuki KUROKAWA
  • Patent number: 11515873
    Abstract: A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: November 29, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Yoshiyuki Kurokawa