Patents by Inventor Hajime Kimura

Hajime Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230350563
    Abstract: A data processing device which includes a flexible position input portion for sensing proximity or a touch of an object such as a user's palm and finger. In the case where a first region of the flexible position input portion is held by a user for a certain period, supply of image signals to the first region is selectively stopped.
    Type: Application
    Filed: June 21, 2023
    Publication date: November 2, 2023
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Hideaki KUWABARA, Koji DAIRIKI
  • Publication number: 20230352491
    Abstract: An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.
    Type: Application
    Filed: July 10, 2023
    Publication date: November 2, 2023
    Inventors: Atsushi UMEZAKI, Hajime KIMURA
  • Patent number: 11803092
    Abstract: It is an object to provide a liquid crystal display device which has excellent viewing angle characteristics and higher quality. The present invention has a pixel including a first switch, a second switch, a third switch, a first resistor, a second resistor, a first liquid crystal element, and a second liquid crystal element. A pixel electrode of the first liquid crystal element is electrically connected to a signal line through the first switch. The pixel electrode of the first liquid crystal element is electrically connected to a pixel electrode of the second liquid crystal element through the second switch and the first resistor. The pixel electrode of the second liquid crystal element is electrically connected to a Cs line through the third switch and the second resistor. A common electrode of the first liquid crystal element is electrically connected to a common electrode of the second liquid crystal element.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: October 31, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 11803074
    Abstract: A touch panel which is thin, has a simple structure, or is easily incorporated into an electronic device is provided. The touch panel includes a first substrate, a second substrate, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, liquid crystal, and an FPC. The first conductive layer has a function of a pixel electrode. The second conductive layer has a function of a common electrode. The third and fourth conductive layers each have a function of an electrode of a touch sensor. The FPC is electrically connected to the fourth conductive layer. The first, second, third, and fourth conductive layers and the liquid crystal are provided between the first and second substrates. The first, second, and third conductive layers are provided over the first substrate. The FPC is provided over the first substrate.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: October 31, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Shunpei Yamazaki
  • Publication number: 20230335073
    Abstract: A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.
    Type: Application
    Filed: June 22, 2023
    Publication date: October 19, 2023
    Inventors: Hajime KIMURA, Atsushi UMEZAKI
  • Publication number: 20230335173
    Abstract: A semiconductor device with low power consumption that is capable of non-destructive reading is provided. The semiconductor device includes a first transistor, a second transistor, a third transistor, a first FTJ element, and a second FTJ element. A first terminal of the first transistor is electrically connected to an output terminal of the first FTJ element, an input terminal of the second FTJ element, and a gate of the second transistor. A first terminal of the second transistor is electrically connected to a second terminal of the third transistor. For data writing, polarization is caused in each of the first FTJ element and the second FTJ element in accordance with data.
    Type: Application
    Filed: September 8, 2021
    Publication date: October 19, 2023
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Hitoshi KUNITAKE
  • Patent number: 11789306
    Abstract: In a semi-transmission liquid crystal display device, two resist masks are required to form a reflective electrode and a transparent electrode; therefore, cost is high. A transparent electrode and a reflective electrode which function as a pixel electrode are stacked. A resist pattern which includes a region having a thick film thickness and a region having a thinner film thickness than the aforementioned region is formed over the reflective electrode by using a light exposure mask which includes a semi-transmission portion. The reflective electrode and the transparent electrode are formed by using the resist pattern. Therefore, the reflective electrode and the transparent electrode can be formed by using one resist mask.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: October 17, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Publication number: 20230326503
    Abstract: A semiconductor device that has reduced power consumption and is capable of non-destructive reading is provided. The semiconductor device includes a first circuit including a first transistor and a first FTJ element, and a second circuit including a second transistor and a second FTJ element. A first terminal of the first transistor is electrically connected to an output terminal of the first FTJ element, and a first terminal of the second transistor is electrically connected to an input terminal of the second FTJ element. A second terminal of the first transistor and a second terminal of the second transistor are electrically connected to a read circuit. In a data writing method, a voltage is applied between the input terminal and the output terminal of each of the first FTJ element and the second FTJ element to polarize the first FTJ element and the second FTJ element.
    Type: Application
    Filed: September 13, 2021
    Publication date: October 12, 2023
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Hideki UOCHI, Atsushi MIYAGUCHI, Tatsunori INOUE
  • Publication number: 20230320099
    Abstract: An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 5, 2023
    Inventors: Hajime KIMURA, Tatsunori INOUE
  • Publication number: 20230317741
    Abstract: A semiconductor device that is less influenced by variations in characteristics between transistors or variations in a load, and is efficient even for normally-on transistors is provided. The semiconductor device includes at least a transistor, two wirings, three switches, and two capacitors. A first switch controls conduction between a first wiring and each of a first electrode of a first capacitor and a first electrode of a second capacitor. A second electrode of the first capacitor is connected to a gate of the transistor. A second switch controls conduction between the gate and a second wiring. A second electrode of the second capacitor is connected to one of a source and a drain of the transistor. A third switch controls conduction between the one of the source and the drain and each of the first electrode of the first capacitor and the first electrode of the second capacitor.
    Type: Application
    Filed: February 16, 2023
    Publication date: October 5, 2023
    Inventor: Hajime KIMURA
  • Publication number: 20230317813
    Abstract: It is an object to provide a semiconductor device with low wiring resistance, high transmittance, or a high aperture ratio. A gate electrode, a semiconductor layer, and a source electrode and a drain electrode are formed using a material having a light-transmitting property and a wiring such as a gate wiring or a source wiring is formed using a material whose resistivity is lower than that of the material having a light-transmitting property. Alternatively, the source wiring and/or the gate wiring are/is formed by a stack of a material having a light-transmitting property and a material whose resistivity is lower than that of the material having a light-transmitting property.
    Type: Application
    Filed: June 2, 2023
    Publication date: October 5, 2023
    Inventor: Hajime KIMURA
  • Patent number: 11776586
    Abstract: A semiconductor device capable of product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding portion and a first transistor, and the second circuit includes a second holding portion and a second transistor. The first and second circuits are each electrically connected to first and second input wirings and first and second wirings. The first holding portion has a function of holding a first current flowing through the first transistor, and the second holding portion has a function of holding a second current flowing through the second transistor. The first and second currents are determined in accordance with first data. When a potential corresponding to second data is input to the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: October 3, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Yoshiyuki Kurokawa
  • Publication number: 20230309308
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.
    Type: Application
    Filed: March 31, 2023
    Publication date: September 28, 2023
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Takanori MATSUZAKI, Kiyoshi KATO, Satoru OKAMOTO
  • Patent number: 11769462
    Abstract: A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/?m (1×10?18 A/?m) or less. Therefore, the drive capability of the semiconductor device can be improved.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: September 26, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsushi Umezaki, Hajime Kimura
  • Publication number: 20230298517
    Abstract: A semiconductor device includes first to tenth transistors and first to fourth capacitors. Gates of the first and the fourth transistors are electrically connected to each other. First terminals of the first, second, fifth, and eighth transistors are electrically connected to a first terminal of the fourth capacitor. A second terminal of the fifth transistor is electrically connected to a gate of the sixth transistor and a first terminal of the second capacitor. A second terminal of the eighth transistor is electrically connected to a gate of the ninth transistor and a first terminal of the third capacitor. Gates of the second, seventh, and tenth transistors are electrically connected to first terminals of the third and fourth transistors and a first terminal of the first capacitor. First terminals of the sixth and seventh transistors are electrically connected to a second terminal of the second capacitor.
    Type: Application
    Filed: May 19, 2023
    Publication date: September 21, 2023
    Inventors: Hajime KIMURA, Takayuki IKEDA
  • Publication number: 20230298650
    Abstract: Provided is a semiconductor device capable of retaining data for a long time. The semiconductor device includes a cell provided with a capacitor, a first transistor, and a second transistor; the capacitor includes a first electrode, a second electrode, and a ferroelectric layer; the ferroelectric layer is provided between the first electrode and the second electrode and polarization reversal occurs by application of a first saturated polarization voltage or a second saturated polarization voltage whose polarity is different from that of the first saturated polarization voltage; and the first electrode, one of a source and a drain of the first transistor, and a gate of the second transistor are electrically connected to one another. In a first period, the first saturated polarization voltage is applied to the ferroelectric layer.
    Type: Application
    Filed: July 20, 2021
    Publication date: September 21, 2023
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Hitoshi KUNITAKE
  • Publication number: 20230299209
    Abstract: A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is controlled with a signal held in the capacitor and a signal output from the inverter so that voltage is supplied to the display element. The inverter and the switch can be constituted by transistors with the same polarity. A semiconductor layer included in the pixel may be formed using a light-transmitting material. Moreover, a gate electrode, a drain electrode, and a capacitor electrode may be formed using a light-transmitting conductive layer. The pixel is formed using a light-transmitting material in such a manner, whereby the display device can be a transmissive display device while including a pixel having a memory.
    Type: Application
    Filed: April 20, 2023
    Publication date: September 21, 2023
    Inventors: Hajime KIMURA, Kengo AKIMOTO, Masashi TSUBUKU, Toshinari SASAKI
  • Patent number: 11754881
    Abstract: The present invention has a pixel which includes a first switch, a second switch, a third switch, a first resistor, a second resistor, a first liquid crystal element, and a second liquid crystal element. A pixel electrode of the first liquid crystal element is electrically connected to a signal line through the first switch. The pixel electrode of the first liquid crystal element is electrically connected to a pixel electrode of the second liquid crystal element through the second switch and the first resistor. The pixel electrode of the second liquid crystal element is electrically connected to a Cs line through the third switch and the second resistor. A common electrode of the first liquid crystal element is electrically connected to a common electrode of the second liquid crystal element.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: September 12, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 11755285
    Abstract: A semiconductor device including a multiplier circuit is provided. A first cell, a second cell, and a first circuit are included. The first cell includes a first transistor. The second cell includes a second transistor. The first circuit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and a first switch.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: September 12, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime Kimura, Takahiro Fukutome
  • Publication number: 20230282679
    Abstract: To improve color reproduction areas in a display device having light-emitting elements. A display region has a plurality of picture elements. Each picture element includes: first and second pixels each including a light-emitting element which has a chromaticity whose x-coordinate in a CIE-XY chromaticity diagram is 0.50 or more; third and fourth pixels each including a light-emitting element which has a chromaticity whose y-coordinate in the diagram is 0.55 or more; and fifth and sixth pixels each including a light-emitting element which has a chromaticity whose x-coordinate and y-coordinate in the diagram are 0.20 or less and 0.25 or less, respectively. The light-emitting elements in the first and second pixels have different emission spectrums from each other; the light-emitting elements in the third and fourth pixels have different emission spectrums from each other, and the light-emitting elements in the fifth and sixth pixels have different emission spectrums from each other.
    Type: Application
    Filed: May 11, 2023
    Publication date: September 7, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Atsushi MIYAGUCHI