Patents by Inventor Hajime Matsuda
Hajime Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8714455Abstract: There is provided an external illumination apparatus capable of increasing flexibility of illumination, the external illumination apparatus including a CPU and a memory so as to control lighting of a plurality of illumination LEDs with reference to a lighting pattern stored in the memory, wherein this lighting control is executed by a lighting command from an optical information reading apparatus.Type: GrantFiled: August 9, 2011Date of Patent: May 6, 2014Assignee: Keyence CorporationInventors: Hajime Matsuda, Tomomi Izaki, Daisuke Matsumoto
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Publication number: 20140048603Abstract: There is provided an external illumination apparatus capable of increasing flexibility of illumination, the external illumination apparatus including a CPU and a memory so as to control lighting of a plurality of illumination LEDs with reference to a lighting pattern stored in the memory, wherein this lighting control is executed by a lighting command from an optical information reading apparatus.Type: ApplicationFiled: October 25, 2013Publication date: February 20, 2014Applicant: Keyence CorporationInventors: Hajime Matsuda, Tomomi Izaki, Daisuke Matsumoto
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Patent number: 8479991Abstract: There is provided an illumination setting support apparatus that enables a user to easily set an optimal lighting pattern while visually checking. A schematic diagram of the illumination unit is displayed in the setting screen, so that clicking on a desired area inside this schematic diagram allows the arbitrary area to be selected from eight areas in the circumferential row of the “outermost circumference” of the external illumination unit. Lighting pattern information is transmitted to a bar code reader and is transferred to the external illumination unit. Imaging is performed while executing illumination control in accordance with the lighting pattern to thereby immediately display a live image on a PC.Type: GrantFiled: November 26, 2012Date of Patent: July 9, 2013Assignee: Keyence CorporationInventors: Shigeo Nakamura, Hajime Matsuda
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Patent number: 8342404Abstract: There is provided an illumination setting support apparatus that enables a user to easily set an optimal lighting pattern while visually checking. A schematic diagram of the illumination unit is displayed in the setting screen, so that clicking on a desired area inside this schematic diagram allows the arbitrary area to be selected from eight areas in the circumferential row of the “outermost circumference” of the external illumination unit. Lighting pattern information is transmitted to a bar code reader and is transferred to the external illumination unit. Imaging is performed while executing illumination control in accordance with the lighting pattern to thereby immediately display a live image on a PC.Type: GrantFiled: August 9, 2011Date of Patent: January 1, 2013Assignee: Keyence CorporationInventors: Shigeo Nakamura, Hajime Matsuda
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Publication number: 20120182374Abstract: In order to improve read stability, a printing condition is set based on not visual read of a user, but read with an optical information reading apparatus. A printing quality evaluation apparatus includes: an image acquiring section that acquires an image; a symbol extracting section that extracts the symbol in which the printing quality can be evaluated from the captured images acquired by the image acquiring section; a printing quality evaluation section that evaluates the printing quality of the symbol extracted by the symbol extracting section; an identification information recognition section that recognizes the identification information identifying each printing condition of the symbol; and an evaluation output section that outputs the identification information, which is recognized by the identification information recognition section, and an evaluation result of the printing quality of the printing quality evaluation section according to the symbol extracted by the symbol extracting section.Type: ApplicationFiled: January 12, 2012Publication date: July 19, 2012Applicant: Keyence CorporationInventors: Hajime Matsuda, Takaaki Ito
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Patent number: 8188520Abstract: A method for fabricating a field effect transistor includes: forming an insulating film provided on a semiconductor layer, the insulating film having an opening via which a surface of the semiconductor layer is exposed and including silicon oxide; forming a Schottky electrode on the insulating film and in the opening, the Schottky electrode having an overhang portion and having a first contact layer that is provided in a region contacting the insulating film and contains oxygen, and a second contact layer that is provided on the first contact layer and contains a smaller content of oxygen than that of the first contact layer; and removing the insulating film by a solution including hydrofluoric acid.Type: GrantFiled: May 10, 2011Date of Patent: May 29, 2012Assignee: Eudyna Devices Inc.Inventors: Tadashi Watanabe, Hajime Matsuda
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Patent number: 8172143Abstract: Provided is a code reading device capable of reducing a time from start of reading of a symbol code until a decoded result is transmitted to an external device. The code reading device includes first and second CPUs that access a shared memory, an imaging element that optically reads the symbol code to generate a read image, and a DMAC that transfers the read image from the imaging element to the shared memory. The first CPU decodes the read image in the shared memory based on a command of the second CPU. The second CPU selectively executes any one of an imaging control task, a decode control task, and a decoded result transmission task, in which the imaging control task is given priority over the decode control task, and the decode control task is given priority over the decoded result transmission task.Type: GrantFiled: June 6, 2011Date of Patent: May 8, 2012Assignee: Keyence CorporationInventors: Hajime Matsuda, Shigeo Nakamura
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Publication number: 20120068629Abstract: There is provided an external illumination apparatus capable of increasing flexibility of illumination, the external illumination apparatus including a CPU and a memory so as to control lighting of a plurality of illumination LEDs with reference to a lighting pattern stored in the memory, wherein this lighting control is executed by a lighting command from an optical information reading apparatus.Type: ApplicationFiled: August 9, 2011Publication date: March 22, 2012Applicant: KEYENCE CORPORATIONInventors: Hajime Matsuda, Tomomi Izaki, Daisuke Matsumoto
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Publication number: 20120067952Abstract: Quality of a code provided in a test piece of a work is evaluated, using a sample processing function of a marker that gives the code to the work to present suggestion for setting of a processing condition to a user. Images picked up by a bar code reader are taken in to create a list of readable codes from these picked-up images, and images of these readable codes are displayed in a list. Tuning processing is performed to all the listed-up codes. In this tuning processing, the reading is tried while changing brightness, and a barometer of readability (easiness of decoding) in each of the reading trials is found to calculate a score indicating a level of reading stability based on a value of integral of this barometer, and this score is displayed as a numeric value and in a graph.Type: ApplicationFiled: August 9, 2011Publication date: March 22, 2012Applicant: KEYENCE CORPORATIONInventor: Hajime Matsuda
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Publication number: 20120067957Abstract: There is provided an illumination setting support apparatus that enables a user to easily set an optimal lighting pattern while visually checking. A schematic diagram of the illumination unit is displayed in the setting screen, so that clicking on a desired area inside this schematic diagram allows the arbitrary area to be selected from eight areas in the circumferential row of the “outermost circumference” of the external illumination unit. Lighting pattern information is transmitted to a bar code reader and is transferred to the external illumination unit. Imaging is performed while executing illumination control in accordance with the lighting pattern to thereby immediately display a live image on a PC.Type: ApplicationFiled: August 9, 2011Publication date: March 22, 2012Applicant: KEYENCE CORPORATIONInventors: Shigeo Nakamura, Hajime Matsuda
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Publication number: 20110309148Abstract: Provided is a code reading device capable of reducing a time from start of reading of a symbol code until a decoded result is transmitted to an external device. The code reading device includes first and second CPUs that access a shared memory, an imaging element that optically reads the symbol code to generate a read image, and a DMAC that transfers the read image from the imaging element to the shared memory. The first CPU decodes the read image in the shared memory based on a command of the second CPU. The second CPU selectively executes any one of an imaging control task, a decode control task, and a decoded result transmission task, in which the imaging control task is given priority over the decode control task, and the decode control task is given priority over the decoded result transmission task.Type: ApplicationFiled: June 6, 2011Publication date: December 22, 2011Applicant: KEYENCE CORPORATIONInventors: Hajime Matsuda, Shigeo Nakamura
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Publication number: 20110215383Abstract: A method for fabricating a field effect transistor includes: forming an insulating film provided on a semiconductor layer, the insulating film having an opening via which a surface of the semiconductor layer is exposed and including silicon oxide; forming a Schottky electrode on the insulating film and in the opening, the Schottky electrode having an overhang portion and having a first contact layer that is provided in a region contacting the insulating film and contains oxygen, and a second contact layer that is provided on the first contact layer and contains a smaller content of oxygen than that of the first contact layer; and removing the insulating film by a solution including hydrofluoric acidType: ApplicationFiled: May 10, 2011Publication date: September 8, 2011Applicant: EUDYNA DEVICES INC.Inventors: Tadashi Watanabe, Hajime Matsuda
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Patent number: 7964486Abstract: A method for fabricating a field effect transistor includes: forming an insulating film provided on a semiconductor layer, the insulating film having an opening via which a surface of the semiconductor layer is exposed and including silicon oxide; forming a Schottky electrode on the insulating film and in the opening, the Schottky electrode having an overhang portion and having a first contact layer that is provided in a region contacting the insulating film and contains oxygen, and a second contact layer that is provided on the first contact layer and contains a smaller content of oxygen than that of the first contact layer; and removing the insulating film by a solution including hydrofluoric acid.Type: GrantFiled: February 7, 2008Date of Patent: June 21, 2011Assignee: Eudyna Devices Inc.Inventors: Tadashi Watanabe, Hajime Matsuda
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Patent number: 7821031Abstract: A switch circuit includes: a first FET that is connected to one of an input terminal and an output terminal, and performs ON/OFF operation under the control of a gate electrode connected to a control terminal; and a second FET that is connected between the first FET and the other one of the input terminal and the output terminal, and performs ON/OFF operation under the control of a gate electrode connected to the control terminal. The first FET has a higher gate backward breakdown voltage than that of the second FET. Alternatively, the first FET has lower OFF capacitance than that of the second FET.Type: GrantFiled: March 29, 2006Date of Patent: October 26, 2010Assignee: Eudyna Devices Inc.Inventor: Hajime Matsuda
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Patent number: 7662421Abstract: In the container-packed, oil-in-water type emulsified food product in accordance with the present invention, an oil-in-water type emulsified food comprises edible oils and fats, vinegar and egg yolk, and is packed and sealed in a container with an oxygen barrier property and has a dissolved oxygen concentration immediately after manufacturing is 0.8 to 8.1% O2. This container-packed, oil-in-water type emulsified food product demonstrates excellent flavor balance and small degradation of quality caused by oxidation during storage.Type: GrantFiled: March 18, 2003Date of Patent: February 16, 2010Assignee: Q.P. CorporationInventors: Hideaki Kobayashi, Masahiro Ariizumi, Yasuhiko Shigematsu, Mitsuru Takamiya, Hajime Matsuda, Nobuhisa Sakabe
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Publication number: 20090272809Abstract: Reading result information about whether bar code information has been able to be read normally in a scanning cycle unit is stored in association with a plurality of locations and information on a condition set upon reading. When it is determined, based on stored reading result information which is obtained in an immediately previous scanning cycle, that bar code information in an identical relative location in the immediately previous scanning cycle has been able to be read normally, information on a condition set upon reading in the immediately previous scanning cycle is read. When it is determined that bar code information has not been able to be read normally, information on a condition that differs from information on a condition set upon reading in the immediately previous scanning cycle is set.Type: ApplicationFiled: April 9, 2009Publication date: November 5, 2009Applicant: Keyence CorporationInventor: Hajime Matsuda
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Publication number: 20080211052Abstract: A method for fabricating a field effect transistor includes: forming an insulating film provided on a semiconductor layer, the insulating film having an opening via which a surface of the semiconductor layer is exposed and including silicon oxide; forming a Schottky electrode on the insulating film and in the opening, the Schottky electrode having an overhang portion and having a first contact layer that is provided in a region contacting the insulating film and contains oxygen, and a second contact layer that is provided on the first contact layer and contains a smaller content of oxygen than that of the first contact layer; and removing the insulating film by a solution including hydrofluoric acid.Type: ApplicationFiled: February 7, 2008Publication date: September 4, 2008Applicant: EUDYNA DEVICES INC.Inventors: Tadashi WATANABE, Hajime MATSUDA
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Publication number: 20080174357Abstract: A semiconductor device having a switch includes a first FET connected to a terminal and a second FET of a stage following that of the first FET. The gate width of the first FET is greater than that of the second FET. A sum of lengths of a source electrode and a drain electrode of the first FET in a direction perpendicular to the gate width of the first FET is smaller than a sum of lengths of a source electrode and a drain electrode of the second FET in a direction perpendicular to the gate width of the second FET.Type: ApplicationFiled: January 23, 2008Publication date: July 24, 2008Applicant: EUDYNA DEVICES INC.Inventor: Hajime MATSUDA
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Publication number: 20060219534Abstract: A switch circuit includes: a first FET that is connected to one of an input terminal and an output terminal, and performs ON/OFF operation under the control of a gate electrode connected to a control terminal; and a second FET that is connected between the first FET and the other one of the input terminal and the output terminal, and performs ON/OFF operation under the control of a gate electrode connected to the control terminal. The first FET has a higher gate backward breakdown voltage than that of the second FET. Alternatively, the first FET has lower OFF capacitance than that of the second FET.Type: ApplicationFiled: March 29, 2006Publication date: October 5, 2006Applicant: EUDYNA DEVICES INC.Inventor: Hajime Matsuda
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Patent number: 7087957Abstract: A semiconductor device includes a compound semiconductor substrate, a channel layer provided on the compound semiconductor substrate, a buried layer provided on the channel layer, a first recess formed in the buried layer in an E-mode region, a second recess formed in the first recess in the E-mode region and another second recess formed in the buried layer in a D-mode region, and a gate electrode provided in the second recess in the E-mode region and another gate electrode provided in the second recess in the D-mode region, and a distance between a surface of the buried layer and a bottom of the second recess in the E-mode region is shorter than another distance between another surface of the buried layer and a bottom of said another second recess in the D-mode region.Type: GrantFiled: January 14, 2005Date of Patent: August 8, 2006Assignee: Eudyna Devices, Inc.Inventor: Hajime Matsuda