Patents by Inventor Han Choon Lee

Han Choon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7307017
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device includes a silicon substrate, a source region and a drain region. A gate electrode is formed on the silicon substrate. Also, a metal silicide layer is formed on each of the gate electrode, the source region, and the drain region. The metal silicide layer has a thickness uniformity of about 1˜20%. A disclosed fabrication method includes forming a metal layer on a silicon substrate having a gate electrode, a source region, and a drain region; performing a plasma treatment on the metal layer; forming a protective layer on the metal layer; and heat treating the silicon substrate on which the protective layer is formed to thereby form a metal silicide layer. A gas that includes nitrogen is used as a plasma gas during the plasma treatment.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: December 11, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventors: Han-Choon Lee, Jin-Woo Park
  • Publication number: 20070166985
    Abstract: A method for fabricating a thin layer in a semiconductor device is provided. The method can include: forming a preliminary layer, in which Ta and F are mixed, on a semiconductor substate by performing an Atomic Layer Deposition (ALD) method; forming a Ta layer by reacting the preliminary layer with B2H6; and forming a TaN layer by performing heat treatment for the Ta layer in N2 atmosphere.
    Type: Application
    Filed: December 21, 2006
    Publication date: July 19, 2007
    Inventor: Han Choon Lee
  • Publication number: 20070166987
    Abstract: A method for forming a metal line of a semiconductor device includes forming an interlayer insulation film over a semiconductor substrate, forming a trench for exposing at least a portion of the semiconductor substrate by using a selective etching process, and forming a diffusion barrier layer over the interlayer film and the inner walls of the trench, by using a plasma enhanced atomic layer deposition process in which a high frequency power generator is set to have a frequency of 13.56 MHz. The plasma enhanced atomic layer deposition process is performed with a base pressure in a chamber maintained at 1×10?8 to 3×10?7 torr.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 19, 2007
    Inventors: In-Cheol Baek, Han-Choon Lee
  • Publication number: 20070161241
    Abstract: A method for forming a thin film of a semiconductor device is provided. The method includes forming a TaN film on a semiconductor substrate, and converting a portion of the TaN film into a Ta film by reacting the TaN film with NO2. The Ta film is formed to have a thickness which is about half of the thickness of the TaN film.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 12, 2007
    Inventor: Han-Choon Lee
  • Publication number: 20070155163
    Abstract: A method for forming a thin film of a semiconductor device is provided. The method includes forming a TaN film on a semiconductor substrate by employing an atomic layer deposition method; and converting a part of the TaN film into a Ta by reacting the TaN film with NO2 to form a Ta film. The NO2 is formed by reacting NH3 with O2.
    Type: Application
    Filed: December 19, 2006
    Publication date: July 5, 2007
    Inventors: In-Cheol Baek, Han-Choon Lee
  • Publication number: 20070152334
    Abstract: A semiconductor device includes a semiconductor substrate, an interlayer insulating film formed over the substrate, a trench formed in the interlayer insulating film, a cover film formed over the inside surface of the trench, a barrier layer formed over the cover film; and a metal line formed over the barrier layer which fills and seals the trench. The metal line is in direct contact with the semiconductor substrate.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 5, 2007
    Inventor: Han-Choon Lee
  • Publication number: 20070152341
    Abstract: A method for forming a copper metal wiring by using a damascene process, which includes the steps of: forming a damascene pattern on an interlayer insulating film on a semiconductor substrate; forming a barrier metal layer inside the damascene pattern; forming a copper layer in the damascene pattern; and forming a capping metal layer on the copper layer. Particularly, a top surface of the copper layer is buried in the damascene pattern to be lower than a top surface of the interlayer insulating film.
    Type: Application
    Filed: December 19, 2006
    Publication date: July 5, 2007
    Inventors: Jong-Taek Hwang, Han-Choon Lee
  • Publication number: 20070152336
    Abstract: A semiconductor device and method of manufacturing same, capable of preventing the material of a barrier metal layer from penetrating into an intermetallic insulating layer are provided. In an embodiment, the device can include: a first metal interconnection formed in a lower insulating layer on a semiconductor substrate; an intermetallic insulating layer formed on the lower insulating layer including the first metal interconnection, the intermetallic insulating layer having a via hole and a trench for a second metal interconnection connecting to the first metal interconnection; a carbon implantation layer formed on inner walls of the via hole and the trench of the intermetallic insulating layer; a barrier metal layer deposited on the first metal interconnection exposed through the via hole and on the carbon implantation layer; a via formed in the via hole; and the second metal interconnection formed in the trench.
    Type: Application
    Filed: December 20, 2006
    Publication date: July 5, 2007
    Inventors: Han Choon Lee, Kyung Min Park, Cheon Man Shim
  • Publication number: 20070155169
    Abstract: A method for forming a thin film of a semiconductor device, which may include at least one of the following steps: Forming a Tantalum Nitride (TaN) film over a semiconductor substrate by atomic layer deposition. Forming a Tantalum (Ta) film by converting at least a portion of a Tantalum Nitride (TaN) film into Tantalum (Ta) by soaking the TaN film in a diluted HNO3 solution.
    Type: Application
    Filed: December 1, 2006
    Publication date: July 5, 2007
    Inventors: In-Cheol Baek, Han-Choon Lee
  • Publication number: 20070152333
    Abstract: Disclosed are a metal interconnection of a semiconductor device and a method of fabricating the same. The metal interconnection includes an interlayer dielectric layer formed having a trench on a semiconductor layer, a first TaN layer formed at an inner wall of the trench, a second TaN layer formed on the first TaN layer, and a conductive material filling the trench, wherein TaN of the first TaN layer has a grain size smaller than a grain size of TaN of the second TaN layer.
    Type: Application
    Filed: December 26, 2006
    Publication date: July 5, 2007
    Inventor: Han Choon Lee
  • Publication number: 20070141833
    Abstract: Provided is a method for manufacturing a semiconductor device. An insulation layer is formed on a bottom structure of a semiconductor substrate. Then, a trench and a via hole are formed by selectively etching the insulation layer, and a copper layer is deposited to fill the via hole and the trench. Next, a copper line is formed by a CMP (chemical mechanical polishing) process to planarize the copper layer, and a plasma process is performed to form a plasma-treated surface layer of the semiconductor substrate. The plasma-treated surface layer is then removed.
    Type: Application
    Filed: November 27, 2006
    Publication date: June 21, 2007
    Inventors: Sang Chul Kim, Han Choon Lee
  • Publication number: 20070141735
    Abstract: A method for monitoring a deposition temperature of a Cu seed layer by measuring an optical reflectivity of the Cu seed layer deposited on a substrate; and estimating the deposition temperature of the Cu seed layer by comparing the measured optical reflectivity with a reference optical reflectivity of a reference Cu seed layer in which an agglomeration phenomenon has not happened. The estimating step includes computing the deposition temperature of the Cu seed layer at a temperature higher than about ?25° C. which is a reference deposition temperature for depositing the reference Cu seed layer if the measured reflectivity is smaller than the reference optical reflectivity.
    Type: Application
    Filed: December 14, 2006
    Publication date: June 21, 2007
    Inventors: Sung-Joong Joo, Han-Choon Lee
  • Publication number: 20070141839
    Abstract: A method for fabricating a fully silicided gate, including forming a gate dielectric layer on a semiconductor substrate, depositing an amorphous silicon layer on the gate dielectric layer, forming a metallic layer on the amorphous silicon layer, depositing a hard mask on the metallic layer, wherein the amorphous silicon layer and the metal layer are silicided due to a thermal budget applied thereto, thereby forming a metal silicide layer, and patterning the metal silicide layer based on the hard mask to form a gate.
    Type: Application
    Filed: December 15, 2006
    Publication date: June 21, 2007
    Inventors: Dae-Young Kim, Han-Choon Lee
  • Publication number: 20070134915
    Abstract: A method for forming a metal line of a semiconductor device may include cleaning a via and/or a trench with B2H6 gas to remove Fluorine. Cleaning step may be performed at a temperature between approximately 100° C. and approximately 500° C.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 14, 2007
    Inventor: Han-Choon Lee
  • Patent number: 7186646
    Abstract: Semiconductor devices and methods of forming a barrier metal in semiconductor devices are disclosed. A disclosed semiconductor device includes a metal layer on a semiconductor substrate; an interlayer dielectric layer on the metal layer, a hole in the interlayer dielectric layer that exposes a portion of the metal layer; and a barrier metal on inner walls of the hole. The barrier metal is made of TaSiN having a resistivity less than or equal to about 10,000 ?ohm-cm.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: March 6, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Han-Choon Lee
  • Publication number: 20060292862
    Abstract: A method for forming a barrier metal of a semiconductor device includes forming an insulating layer on a semiconductor substrate and forming an opening in the insulating layer and forming a TiSiN layer having a desired thickness by repeatedly performing a process of forming a TiSiN layer having an atomic layer thickness in a reaction chamber. The process of forming a TiSiN layer having an atomic layer thickness includes performing deposition of a SiH4 layer inside the opening and on the insulating layer using an atomic layer deposition process, discharging a gas remaining in the reaction chamber by using an inert gas, performing deposition of a certain precursor layer on the SiH4 layer, and discharging a gas of precursor material remaining in the reaction chamber by using an inert gas. The method of forming a barrier metal further includes performing plasma processing for the TiSiN layer so as to remove impurities contained in the TiSiN layer.
    Type: Application
    Filed: August 30, 2006
    Publication date: December 28, 2006
    Applicant: DONGBU ELECTRONICS CO., LTD.
    Inventor: Han-Choon Lee
  • Patent number: 7122474
    Abstract: A method for forming a barrier metal of a semiconductor device wherein a TiSiN layer having an atomic layer thickness is deposited by performing deposition of an Si layer inside a contact hole of a semiconductor device using an atomic layer deposition process and by performing deposition of a precursor layer on the Si layer. By repetition of this ALD process, the TiSiN layer is thickly formed at a desired thickness. Then, the TiSiN layer is plasma processed under the atmosphere of a nitrogen gas and a hydrogen gas, or an ammonia gas, and thus impurities are removed from the TiSiN layer. Therefore, it is easy to thickly form the TiSiN layer for the barrier metal. It is possible to reduce resistivity of the TiSiN layer to a relatively low level. Thereby, it is possible to decrease a contact resistance of the TiSiN layer and, further, to enhance an electrical characteristic of the semiconductor device.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: October 17, 2006
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Han-Choon Lee
  • Publication number: 20060148246
    Abstract: The present invention provides a method of forming a diffusion barrier layer comprising a TaSiN layer. The method includes depositing a TaN layer into a via hole which penetrates an insulation layer exposing a first metal line layer, and transforming the TaN layer into a TaSiN layer using a radio frequency (RF) power and a (remote) plasma using SiH4 gas. Transforming the TaN layer into a TaSiN layer may include: loading a structure including the TaN layer into a plasma reaction chamber; injecting SiH4 gas into the plasma reaction chamber; and forming the TaSiN layer by reacting Si- or Si atom-containing species with the TaN layer.
    Type: Application
    Filed: December 23, 2005
    Publication date: July 6, 2006
    Inventor: Han-Choon Lee
  • Patent number: 7037836
    Abstract: A semiconductor device which effectively reduces copper oxide layers on copper conductive lines is disclosed. The method includes forming a first insulating layer on a semiconductor substrate; forming a first conductive line by depositing a conductive material on the first insulating layer and selectively patterning the conductive material. A second insulating layer is deposited on top of the substrate including on the first conductive line. A via hole is formed by selectively patterning the second insulating layer to expose a certain portion of the first conductive line. A natural oxide layer is removed by plasma-processing the natural oxide layer using H2+CO gas.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: May 2, 2006
    Assignee: DongbuAnam Semiconductor Inc.
    Inventor: Han Choon Lee
  • Publication number: 20060063395
    Abstract: A method of manufacturing a semiconductor device employs a PEALD method including using an organometallic Ta precursor to form a TaN thin film. As a result, a conformal TaN diffusion barrier may be formed at a temperature of 250° C. or higher, so that impurities are reduced and density is increased in the TaN thin film.
    Type: Application
    Filed: September 15, 2005
    Publication date: March 23, 2006
    Inventor: Han-Choon Lee