Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface; a redistribution layer (RDL) having a surface, wherein the first surface of the first die is on and electrically coupled to the surface of the RDL by non-solder interconnects; and a second die at the second surface of the first die, wherein the second die is electrically coupled directly to the second surface of the first die by solder interconnects.

Abstract: A tri-level digital-to-analog converter (DAC) element includes a first DAC cell. The first DAC cell includes a first reference circuit, a second reference circuit, and a switch circuit. The first reference circuit provides a first reference signal. The second reference circuit provides a second reference signal. The first switch circuit receives a control input from an input port of the tri-level DAC element, and controls interconnection between the first reference circuit, the second reference circuit, and an output port of the tri-level DAC element according to the control input. During a period in which the tri-level DAC element operates in a “0” state, the first switch circuit is arranged to couple at least one of the first reference circuit and the second reference circuit to the output port of the tri-level DAC element.

Abstract: A joint pilot detection method includes: obtaining a plurality of input signals that are derived from a plurality of satellite signals transmitted from a plurality of global navigation satellite system (GNSS) satellites, respectively, wherein each of the plurality of satellite signals carries a pilot component modulated by a secondary code; obtaining a plurality of code sequences that are replicas of secondary codes of the plurality of satellites, respectively; performing a plurality of correlation operations according to the plurality of input signals and the plurality of code sequences, for generating a plurality of correlation results, respectively; and performing pilot detection by jointly considering the plurality of correlation results.

Abstract: An amplifier circuit includes a voltage-to-current conversion circuit and a current-to-voltage conversion circuit. The voltage-to-current conversion circuit generates a current signal according to an input voltage signal, and includes an operational transconductance amplifier (OTA) used to output the current signal at an output port of the OTA. The current-to-voltage conversion circuit generates an output voltage signal according to the current signal, and includes a linear amplifier (LA), wherein an input port of the LA is coupled to the output port of the OTA, and the output voltage signal is derived from an output signal at an output port of the LA.

Abstract: The application provides a sense amplifier and an operation method thereof. The operation method for the sense amplifier includes: during a first phase, initializing a first sensing input voltage and a second input sensing voltage; and recording a first sensing output voltage and a second sensing output voltage of a previous round by charges stored in a plurality of transistors of the sense amplifier; during a second phase, sampling the first sensing output voltage and the second sensing output voltage of a current round as a plurality of transit points; during a first sub-phase of a third phase, amplifying a voltage difference between an input signal and a first reference voltage; and during a second sub-phase of the third phase, pulling the first sensing output voltage and the second sensing output voltage into a full-swing voltage range, and recording charges to the transistors of the sense amplifier.

Abstract: An antenna package structure is provided. The antenna package structure includes a glass substrate, an interconnect structure, a plurality of semiconductor chips, and an antenna array structure. The glass substrate has a first surface and a second surface opposite to the first surface. The interconnect structure is disposed over the first surface of the glass substrate. The plurality of semiconductor chips are mounted over the interconnect structure. The antenna array structure is formed on the second surface of the glass substrate. Furthermore, the plurality of semiconductor chips are coupled to the antenna array structure through the interconnect structure and the glass substrate.

Abstract: The panel driving circuit includes a channel circuit, first pads, first switches, a second pad, and at least one second switch. The first pads are configured to be electrically connected to data lines of a cholesteric liquid crystal (CHLC) panel respectively. Each first switch has a first terminal electrically connected to the channel circuit, and a second terminal electrically connected to one of the first pads. Each second switch has a first terminal electrically connected to the second pad, and a second terminal electrically connected to the first pads. In a pixel charging period, the first switches are turned on, and the second switch is turned off. In a test period, the first switch is turned off, the second switch is turned on, and the second pad is configured to receive a measurement signal for measuring capacitance of pixels in the CHLC panel.

Abstract: A noise filter circuit includes a filter and a transistor off-resistance control circuit. The filter includes a first transistor and a charge storage component. The first transistor has off-resistance when turned off or operated under sub-threshold region. A control terminal of the first transistor is not directly tied to a reference voltage, and is used to receive a first control voltage. The charge storage component has one terminal coupled to a connection terminal of the first transistor. The transistor off-resistance control circuit is coupled to the first transistor, and arranged to set the first control voltage for controlling the off-resistance of the first transistor.

Abstract: The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.

Abstract: An integrated circuit assembly may be formed with a bridge incorporated into at least one level structure of the integrated circuit assembly, which electrically interconnects at least two integrated circuit devices in another level structure of the integrated circuit assembly. In one example, the integrated circuit assembly may include a first level structure that comprises at least a first integrated circuit device and a second integrated circuit device, and a second level structure comprising at least one integrated circuit device electrically attached to the first integrated circuit device of the first level structure and the bridge forming an electrical attachment between the first integrated circuit device of the first level structure and the second integrated circuit device of the first level structure.

Abstract: A brake pad assembly is provided in the present disclosure. The brake pad assembly includes at least one back plate, at least one brake pad, at least one sensor plate and a warning module. The brake pad is on the surface of the board. The brake pad is surrounded by the sensor plate, and the sensor plate forms a closed circuit. The warning module is electrically connected to the sensor plate. A warning signal is generated by the warning module when the closed circuit of the sensor plate forms an open circuit or a short circuit.

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result.

Abstract: A method for printing on a substrate includes printing a support structure by printing a liquid precursor material and curing the liquid precursor material, positioning a substrate within the support structure, printing one or more anchors on the substrate and the support structure by printing and curing the liquid precursor material to secure the substrate to the support structure, and printing one or more device structures on the substrate while anchored by printing and curing the liquid precursor material.

Abstract: The application provides a sense amplifier and an operation method thereof. The operation method for the sense amplifier includes: during a first phase, initializing a first sensing input voltage and a second input sensing voltage; and recording a first sensing output voltage and a second sensing output voltage of a previous round by charges stored in a plurality of transistors of the sense amplifier; during a second phase, sampling the first sensing output voltage and the second sensing output voltage of a current round as a plurality of transit points; during a first sub-phase of a third phase, amplifying a voltage difference between an input signal and a first reference voltage; and during a second sub-phase of the third phase, pulling the first sensing output voltage and the second sensing output voltage into a full-swing voltage range, and recording charges to the transistors of the sense amplifier.

Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

Abstract: A method for displaying real-time battle information is performed by a terminal. The method includes: displaying a user interface of a battle; displaying, within the user interface of the battle, identifiers of user accounts participating in the battle, the identifier of each user account having a display region and the display region comprising a plurality of sub-regions, different sub-regions corresponding to different information categories; and in response to an operation on a target sub-region in a display region of a target identifier, displaying real-time battle information of a target information category of a target user account corresponding to the target identifier, the target information category being an information category corresponding to the target sub-region.

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Abstract: The present invention provides an amplifier system including an audio amplifier and a power converter. The audio amplifier is supplied by at least a first supply voltage and a second supply voltage, and the audio amplifier is configured to receive an audio signal to generate an output signal. The power converter includes only one inductor, and is configured to generate the first supply voltage and the second supply voltage according to an input voltage.

Abstract: The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.