Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. Each vector data is executed with a multiplying-operation, the MSB vector and the LSB vector of each vector data is executed with a first group-counting operation and a second group-counting operation respectively. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, the effective bit number stored by each memory unit is less than 2.

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.

Abstract: A memory device and an operation method thereof are provided. The operation method includes: in a first phase, selecting a global signal line, selecting a first string select line, unselecting a second string select line, selecting a first word line, and unselecting a second word line; sensing during a second phase; in a third phase, keeping voltages of the global signal line, the selected first word line and the unselected second word line, unselecting the first string select line and selecting the second string select line to switch voltages of the first and the second string select lines; and sensing during a fourth phase.

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a plurality of page buffers, storing an input data; a plurality of memory planes coupled to the page buffers, based on received addresses of the memory planes, a plurality of weights stored in the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result.

Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded double-sided dies therein. In certain embodiments, an insulating layer is formed over the substrate by laminating a pre-structured insulating film thereon. The insulating film may be pre-structured by laser ablation to form structures therein, followed by selective curing of sidewalls of the formed structures.

Abstract: Methods, devices, and systems for determining read voltages for memory systems are provided. In one aspect, a memory device includes an array of memory cells, an accumulating circuit, and a controller. Each of the memory cells is coupled to a corresponding word line of multiple word lines and a corresponding bit line of multiple bit lines. The accumulating circuit is configured to: when data stored in a page is read out by applying each of a plurality of read voltages on a word line corresponding to the page, accumulate read-out signals from multiple memory cells in the page to generate a respective output value that corresponds to the accumulated read-out signals for the read voltage. The controller is configured to determine a calibrated read voltage for the page based on the respective output values and the plurality of read voltages.

Abstract: A high-linearity amplifier including a main operational amplifier, a feedback circuit, and a compensation circuit is shown. The feedback circuit couples an output signal of the main operational amplifier to an input port of the main operational amplifier. The compensation circuit couples a former-stage circuit of the amplifier to the input port of the main operational amplifier to compensate for the non-linearity of the feedback circuit. The compensation circuit and the feedback circuit form an inverse paralleling linearization architecture. In the inverse paralleling linearization architecture, a resistor in the feedback circuit corresponds to a resistor in the compensation circuit which is biased in an inversed way in comparison with the corresponding resistor in the feedback circuit.

Abstract: A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.

Abstract: A bonding element and a method for manufacturing the same thereof are provide, wherein the method comprises the following steps: providing a carrier substrate; forming a first metal layer on the carrier substrate; forming a first insulating layer on the first metal layer, wherein the first insulating layer includes a first through hole; forming a first passivation layer and a first conductive layer in the first through hole, wherein the first passivation layer and the first conductive layer in the first through hole form a first connecting bump; forming a first substrate on the first connection bump and the first insulating layer; removing the carrier substrate and the first metal layer to form a first sub-bonding element; and connecting the first sub-bonding element and a second sub-bonding element with a surface of the first passivation of the first connection bump to form the bonding element.

Abstract: The present invention provides a linear amplifier including an amplifier stage, a DC-shifting stage, a compensation network and a power stage. The amplifier stage is configured to generate a first signal and a second signal. The DC-shifting stage is configured to adjust a DC voltage of the first signal and a DC voltage of the second signal to generate an adjusted first signal and an adjusted second signal. The compensation network is configured to generate a first driving signal and a second driving signal according to the first signal, the second signal, the adjusted first signal and the adjusted second signal. The power stage is configured to generate an output signal according to the first driving signal and the second driving signal.

Abstract: The present invention provides an amplifier including an input stage, an amplifier stage, a power stage and a de-gain stage. The input stage is configured to receive an input signal to generate an amplified signal. The amplifier stage is configured to generate a first driving signal and a second driving signal according to the amplified signal. The power stage comprises a first input terminal and a second input terminal, wherein the power stage is coupled to a supply voltage and a ground voltage, for receiving the first driving signal and the second driving signal from the first input terminal and the second input terminal, respectively, and generating an output signal.

Abstract: The present disclosure relates to semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor package devices having a stiffener framed formed thereon. The incorporation of the stiffener frame improves the structural integrity of the semiconductor package devices to mitigate warpage and/or collapse while simultaneously enabling utilization of thinner core substrates for improved signal integrity and power delivery between packaged devices.

Abstract: This disclosure is directed to a method and apparatus for displaying an expression in a virtual scene. The method includes: displaying a virtual scene; displaying an expression selection region at a first target position in the virtual scene in response to a drag operation on an expression addition icon; and displaying the first target expression in the virtual scene in response to a selection operation on a first target expression in a plurality of first candidate expressions.

Abstract: A screen display method and apparatus, a device, a storage medium, and a program product, in the field of application development technologies are provided. The method includes: displaying a display interface of an application running on a terminal device, the display interface displaying a first application screen of a first user account in the application; displaying an account display bar, the account display bar displaying identifiers of a plurality of user accounts participating in a service related to the application; displaying, in response to an operation on an identifier of a target user account among the identifiers of the plurality of user accounts, the identifier of the target user account in the display interface; and displaying a target screen of the target user account in response to the operation on the identifier of the target user account, the target screen being a screen of the target user account in the application.

Abstract: A bonding element and a method for manufacturing the same thereof are provide, wherein the method comprises the following steps: providing a carrier substrate; forming a first metal layer on the carrier substrate; forming a first insulating layer on the first metal layer, wherein the first insulating layer includes a first through hole; forming a first passivation layer and a first conductive layer in the first through hole, wherein the first passivation layer and the first conductive layer in the first through hole form a first connecting bump; forming a first substrate on the first connection bump and the first insulating layer; removing the carrier substrate and the first metal layer to form a first sub-bonding element; and connecting the first sub-bonding element and a second sub-bonding element with a surface of the first passivation of the first connection bump to form the bonding element.

Abstract: The present invention provides an amplifier circuit, wherein the amplifier circuit includes an input terminal, a capacitor, an amplifier, a feedback circuit and an aliasing tone cancellation circuit. The input terminal is configured to receive a first input signal. The capacitor is coupled to the input terminal. The amplifier is configured to receive the input signal through the capacitor to generate an output signal. The feedback circuit is coupled between an input node and an output node of the amplifier, and is configured to generate a feedback signal according to the output signal, wherein the feedback circuit includes a storage block including a switched-capacitor. The aliasing tone cancellation circuit is coupled between the input terminal of the amplifier circuit and the input node of the amplifier, and configured to generate a signal to cancel or reduce an aliasing tone of the feedback signal according to the input signal.

Abstract: An integrated antenna package structure including a chip, a circuit layer, an encapsulant, a coupling end, an insulating layer, a conductive connector, a dielectric substrate, and an antenna is provided. The circuit layer is electrically connected to the chip. The encapsulant is disposed on the circuit layer and covers the chip. The coupling end is disposed on the encapsulant. The insulating layer covers the coupling end. The insulating layer is not externally exposed. The conductive connector penetrates the encapsulant. The coupling end is electrically connected to the circuit layer by the conductive connection. The dielectric substrate is disposed on the encapsulant and covers the coupling end. The antenna is disposed on the dielectric substrate. A manufacturing method of an integrated antenna package structure is also provided.

Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.