Abstract: A stabilizing fixture to hold and stabilize a server contained within different sizes of server cabinets includes a base, a pressing component and an adjusting component. The pressing component is slidably coupled with the base in a first direction. A first pressing surface is defined on the pressing component for pressing a server. The adjusting component includes a screw and a nut. When the screw is rotated relative to the nut, the nut is driven to move in a second direction, and the nut acts on the pressing component to drive the pressing component in the first direction to press the server. As the pressing component moves along the first direction, the distance between the two pressing component changes to accommodate servers of different sizes.

Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

Abstract: A buck-boost switching power circuit comprises a bypass control circuit which configured to determine whether the buck-boost switching power circuit operates in a bypass mode according to a bypass enable signal. When the conversion voltage difference between the input voltage and the output voltage is less than a reference voltage, the bypass control circuit controls to electrically connect the input power source with the output power source, and operates the buck-boost switching power circuit in the bypass phase of the bypass mode. Before and/or after the bypass phase, the bypass control circuit respectively controls the buck-boost switching power circuit to operate in a first transition phase and/or a second transition phase.

Abstract: The present invention discloses a boost converter power stage circuit, comprising: an organic light-emitting diode power management integrated circuit unit, a switched capacitor converter, and a boost converter, wherein, a flying capacitor is used to boost the voltage of the inductor to twice the voltage, and then the positive voltage of the output voltage source is boosted, and then use the switched capacitor converter to output the voltage in order to obtain the conversion of the negative voltage.

Abstract: A constant time buck-boost switching converter includes: a power switch circuit for switching a first terminal of an inductor between an input voltage and a ground, and for switching a second terminal of the inductor between an output voltage and the ground; and a modulation control circuit for generating a buck ramp signal and a boost ramp signal and for controlling the inductor according to comparisons of these two ramp signals with an error amplification signal, so as to convert the input voltage to the output voltage. The average levels of the buck ramp signal and the boost ramp signal are both equal to a product of the output voltage multiplied by a predetermined ratio. The upper limit of the buck ramp signal and the lower limit of the boost ramp signal are both equal to a product of the input voltage multiplied by the predetermined ratio.

Abstract: A method is provided. The method includes: receiving a semiconductor structure having a first material and a second material; performing a first etch on the first material for a first duration under a first etching chemistry; and performing a second etch on the second material for a second duration under a second etching chemistry, wherein the first material includes a first incubation time and the second material includes a second incubation time greater than the first incubation time under the first etching chemistry. The first material includes a third incubation time and the second material includes a fourth incubation time less than the third incubation time under the second etching chemistry.

Abstract: A spatial light modulator device includes an array of spatial light modulator cells located over a substrate. Each of the spatial light modulator cells includes: a layer stack including a phase change material plate, a spacer dielectric material plate that underlies the phase change material plate, and a metallic heater plate underlying the spacer dielectric material plate and including outer sidewalls; and a pair of bottom electrode via structures contacting a respective surface segment of a bottom surface of the metallic heater plate. Each of the outer sidewalls of the metallic heater plate is vertically coincident with a respective sidewall of the spacer dielectric material plate and with a respective sidewall of the phase change material plate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a stack structure over a substrate, and the stack structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked. The method includes forming a dummy gate electrode over the first semiconductor layers and the second semiconductor layers, and forming a gate spacer layer adjacent to the dummy gate electrode. The method includes removing the second semiconductor layers to form a recess between two adjacent first semiconductor layers, and forming a dummy dielectric layer in the recess after the dummy gate electrode is formed. The dummy dielectric layer is between two adjacent first semiconductor layers. The method includes replacing the dummy gate electrode and the dummy dielectric layer with a gate structure.

Abstract: A seismically suspended isolation device is installed in a suspended configuration at a fixed end and comprises a first support module, a second support module, a first displacement suppressing module and a second displacement suppressing module. The first support module includes a first fixing element, a first moving element, and at least one first roller. The first roller is disposed between the first fixing element and the first moving element. The second support module includes a second fixing element, a second moving element, and at least one second roller. The second roller is disposed between the second fixing element and the second moving element. The first support module and the second support module are stacked together in an orthogonal manner, so that the seismically suspended isolation device generates motion in the first direction and the second direction when the seismically suspended isolation device subjected to an external force.

Abstract: A method includes forming a plurality of semiconductor regions on a wafer, placing the wafer in an etching chamber, globally heating the wafer using a heating source, and projecting a laser beam on the wafer. When the wafer is heated by both of the heating source and the laser beam, the plurality of semiconductor regions on the wafer are etched.

Abstract: Described herein are methods and compositions related to whole gene duplication (WGD). Methods are described for detecting and determining the presence of WGD in a sample, including cell free nucleic acids derived from a subject, such as a liquid sample (e.g., blood, plasma), as well as chromosomal instability and genomic alterations. In various embodiments, the aforementioned methods are used in diagnosis, prognosis and treatment. In other embodiments, processing of samples characterized by WGD is described to confer increased accuracy and precision of detection.

Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.

Abstract: Methods and systems are provided for determining a variant of interest by analyzing sizes and sequences of cfDNA fragments obtained from a test sample. The methods and systems provided herein implement processes that synergistically combine size and sequence information, thereby improving specificity and sensitivity of assays over conventional methods.

Abstract: A robot joint torque control system and a load compensation method therefor are provided, which relate to the technical field of robot joint motion control. A mathematical model of the robot joint torque control system is established first. Equivalent transformation is performed on a system functional block diagram thereof, and then it can be seen that load parameters have a great influence on joint torque output. A load compensation controller is designed to effectively eliminate the influence of the load parameters on an output torque of the joint. The system is equivalent to an inertial element on the basis of the compensation, and then a PD controller parameter is adjusted to increase an open-loop gain of the system, so as to increase a system bandwidth and increase a response speed of the joint torque control system, thereby improving performance of the joint torque control system.

Abstract: Method to implement heat dissipation multilayer and reduce thermal boundary resistance for high power consumption semiconductor devices is provided. The heat dissipation multilayer comprises a first crystalline layer that possesses a first phonon frequency range, a second crystalline layer that has a second phonon frequency range which does not overlap with the first phonon frequency range, and an amorphous layer located between the first and second crystalline layers. The amorphous layer has a third phonon frequency range that overlaps both the first and second phonon frequency ranges.

Abstract: A power converter is provided. The power converter includes a housing, a heat dissipation module, and a first circuit board. The housing forms a receiving space, wherein the housing includes a first housing port and a second housing port. The heat dissipation module is detachably connected to the housing, and disposed in the receiving space. The heat dissipation module includes an inner path that communicates the first housing port with the second housing port. Working fluid enters the inner path via the first housing port. The working fluid leaves the inner path via the second housing port. The first circuit board includes a first circuit board body and a first heat source, wherein the first heat source is disposed on the first circuit board body, and the first heat source is thermally connected to the inner path of the heat dissipation module.

Abstract: A seismically suspended isolation device is installed in a suspended configuration at a fixed end and comprises a first support module, a second support module, a first displacement suppressing module and a second displacement suppressing module. The first support module includes a first fixing element, a first moving element, and at least one first roller. The first roller is disposed between the first fixing element and the first moving element. The second support module includes a second fixing element, a second moving element, and at least one second roller. The second roller is disposed between the second fixing element and the second moving element. The first support module and the second support module are stacked together in an orthogonal manner, so that the seismically suspended isolation device generates motion in the first direction and the second direction when the seismically suspended isolation device subjected to an external force.

Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material is received. A plurality of first main etches are performed to the semiconductor structure for a plurality of first durations under the first etching chemistry. A plurality of pumping operations are performed for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches. Each of the first durations is in a range of from about 1 second to about 2.5 seconds.