Patents by Inventor Han Yu

Han Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240122229
    Abstract: A method for comprehensively analyzing and/or evaluating cigarette burning quality index is disclosed. The steps include collecting cigarette burning quality index data, filtering the cigarette burning quality index data, standardizing cigarette data, and measuring cigarette burning quality. The importance of the cigarette burning quality indicators can also be evaluated. The method for comprehensively analyzing and/or evaluating cigarette burning quality indicators can reflect general laws more accurately by maintaining the sample distribution through a singularity detection method, and analyzing correlations of each index with cigarette performance from multiple perspectives, to fuse them into a comprehensive measurement value. The importance ranking and weight of indicators can be obtained more completely and stably.
    Type: Application
    Filed: November 8, 2023
    Publication date: April 18, 2024
    Inventors: Han ZHENG, Jianbo ZHAN, Hao WANG, Zhenhua YU, Xu WANG, Jiao XIE, Ying ZHANG, Tao WANG, Tingting YU, Baoshan YUE
  • Publication number: 20240128324
    Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Chung-Yi Chiu
  • Patent number: 11961564
    Abstract: To program in a nonvolatile memory device including a cell region including first metal pads and a peripheral region including second metal pads and vertically connected to the cell region by the first metal pads and the second metal pads, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Yeon Yu, Kui-Han Ko, Il-Han Park, June-Hong Park, Joo-Yong Park, Joon-Young Park, Bong-Soon Lim
  • Publication number: 20240117147
    Abstract: A preparation method for a silver (Ag) and graphitic carbon nitride (g-C3N4) co-modified zinc oxide (ZnO) nanocomposite material using a polymer network gel method includes: dispersing zinc oxide, bulk graphitic carbon nitride, and a soluble silver salt in water to obtain a first solution; adding glucose, a complexing agent, a polymer monomer, and a cross-linking agent into the first solution to obtain a second solution; performing a heating reaction on the second solution to obtain a three-dimensional network wet gel; drying the three-dimensional network wet gel to obtain a dry gel, and calcining the dry gel to obtain the Ag and g-C3N4 co-modified ZnO nanocomposite material. The preparation method has advantages of low cost, short period and simple steps; and the prepared nanocomposite material can be simultaneously applied to photocatalytic degradation of organic dye pollutants and photoexcitation detection of nitrogen dioxide gas at room temperature.
    Type: Application
    Filed: September 7, 2023
    Publication date: April 11, 2024
    Inventors: Ming Xu, Han Li, Qiuping Zhang, Huan Yuan, Fei Yu, Man Song
  • Publication number: 20240119267
    Abstract: Apparatuses, systems, and techniques to selectively use one or more neural network layers. In at least one embodiment, one or more neural network layers are selectively used based on, for example, one or more iteratively increasing neural network performance metrics.
    Type: Application
    Filed: September 21, 2022
    Publication date: April 11, 2024
    Inventors: Slawomir Kierat, Piotr Karpinski, Mateusz Sieniawski, Pawel Morkisz, Szymon Migacz, Linnan Wang, Chen-Han Yu, Satish Salian, Ashwath Aithal, Alexandru Fit-Florea
  • Patent number: 11951637
    Abstract: A calibration apparatus includes a processor, an alignment device, and an arm. The alignment device captures images in a three-dimensional space, and a tool is arranged on a flange of the arm. The processor records a first matrix of transformation between an end-effector coordinate-system and a robot coordinate-system, and performs a tool calibration procedure according to the images captured by the alignment device for obtaining a second matrix of transformation between a tool coordinate-system and the end-effector coordinate-system. The processor calculates relative position of a tool center point of the tool in the robot coordinate-system based on the first and second matrixes, and controls the TCP to move in the three-dimensional space for performing a positioning procedure so as to regard points in an alignment device coordinate-system as points of the TCP, and calculates the relative positions of points in the alignment device coordinate-system and in the robot coordinate-system.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: April 9, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Cheng-Hao Huang, Shi-Yu Wang, Po-Chiao Huang, Han-Ching Lin, Meng-Zong Li
  • Publication number: 20240112088
    Abstract: Systems and methods are provided for vector-quantized image modeling using vision transformers and improved codebook handling. In particular, the present disclosure provides a Vector-quantized Image Modeling (VIM) approach that involves pretraining a machine learning model (e.g., Transformer model) to predict rasterized image tokens autoregressively. The discrete image tokens can be encoded from a learned Vision-Transformer-based VQGAN (example implementations of which can be referred to as ViT-VQGAN). The present disclosure proposes multiple improvements over vanilla VQGAN from architecture to codebook learning, yielding better efficiency and reconstruction fidelity. The improved ViT-VQGAN further improves vector-quantized image modeling tasks, including unconditional image generation, conditioned image generation (e.g., class-conditioned image generation), and unsupervised representation learning.
    Type: Application
    Filed: November 27, 2023
    Publication date: April 4, 2024
    Inventors: Jiahui Yu, Xin Li, Han Zhang, Vijay Vasudevan, Alexander Yeong-Shiuh Ku, Jason Michael Baldridge, Yuanzhong Xu, Jing Yu Koh, Thang Minh Luong, Gunjan Baid, Zirui Wang, Yonghui Wu
  • Patent number: 11948400
    Abstract: An action detection method based on a human skeleton feature and a storage medium belong to the field of computer vision, and the method includes: for each person, extracting a series of body keypoints in every frame of the video as the human skeleton feature; calculating a body structure center point and approximating rigid motion area by using the human skeleton feature as a calculated value from the skeleton feature state, and predicting an estimated value in the next frame; performing target matching according to the estimated and calculated value, correlating the human skeleton feature belonging to the same target to obtain a skeleton feature sequence, and then correlating features of each keypoint in the temporal domain to obtain a spatial-temporal domain skeleton feature; inputting the skeleton feature into an action detection model to obtain an action category. In the disclosure, the accuracy of action detection is improved.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: April 2, 2024
    Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Li Yu, Han Yu
  • Publication number: 20240105901
    Abstract: In an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Chen-Hua Yu, Keng-Han Lin, Hung-Jui Kuo, Hui-Jung Tsai
  • Publication number: 20240103209
    Abstract: The present disclosure relates to an optical filter and a method of producing the same. In the producing method, a thermal evaporation deposition process of a sacrificial layer, and depositions process of a base layer and a dielectric stack layer are sequentially performed on a substrate having a trench with a specific width, so that the base layer and the dielectric stack layer extend outward to form a solidified structure with a specific length. Next, a fixed layer is affixed to the dielectric stack layer, and the sacrificial layer is removed using a solvent to remove the substrate. As such, structural strength and flatness of the produced optical filter are enhanced, and a volume thereof is reduced, such that the optical filter can be applied to automated processes of miniaturized elements.
    Type: Application
    Filed: September 26, 2023
    Publication date: March 28, 2024
    Inventors: Chi-Ming YU, Zong Han LI, Chin-Pin YEH
  • Publication number: 20240097011
    Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
  • Publication number: 20240081390
    Abstract: A method for testing burning performance of a dark-colored cigarette using a dark-colored cigarette paper is provided. The dark-colored cigarette paper has a grayscale less than 255. The method includes: simulating, by a robotic arm, a cigarette smoking process and environment; acquiring, by a full-vision camera system, an image of a burn line and ash column region of the dark-colored cigarette; and analyzing a burning performance indicator of the dark-colored cigarette according to coordinate information of the burn line and ash column region. The method is based on a surface reflection characteristic of the dark-colored cigarette paper and a principle of optical reflection to light and highlight an edge of the dark-colored cigarette sample by a light source at a certain angle from a side. In this way, the method forms a chromatic aberration to localize the dark-colored cigarette sample, thereby testing the burning performance of the dark-colored cigarette sample.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 14, 2024
    Applicant: CHINA TOBACCO YUNNAN INDUSTRIAL CO., LTD
    Inventors: Han ZHENG, Jianbo ZHAN, Hao WANG, Zhenhua YU, Jiao XIE, Xu WANG, Ying ZHANG, Tao WANG, Baoshan YUE, Tingting YU, Jiang YU, Liwei LI, Jing ZHANG
  • Publication number: 20240086609
    Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.
    Type: Application
    Filed: February 16, 2023
    Publication date: March 14, 2024
    Inventors: Cheng-YU LIN, Chia Chun WU, Han-Chung CHANG, Chih-Liang CHEN
  • Publication number: 20240089062
    Abstract: A wireless communication method and apparatus for handling radio resource collision are provided. The wireless communication method includes receiving a Radio Resource Control (RRC) configuration indicating a first Control Resource Set (CORESET) pool index associated with a Physical Uplink Control Channel (PUCCH) designated to carry Uplink Control Information (UCI); determining whether the PUCCH overlaps one or more Physical Uplink Shared Channels (PUSCHs) in time domain; after determining that the PUCCH overlaps at least one of the one or more PUSCHs in the time domain, multiplexing the UCI on a particular PUSCH of the one or more PUSCHs that is associated with the first CORESET pool index; and transmitting the UCI via the particular PUSCH.
    Type: Application
    Filed: March 31, 2022
    Publication date: March 14, 2024
    Inventors: WAN-CHEN LIN, CHIA-HAO YU, CHIA-HUNG LIN, HAI-HAN WANG
  • Publication number: 20240087891
    Abstract: A method of patterning a substrate includes forming a first line, a second line, and a third line over the substrate, the first line, the second line, and the third line being parallel in a plan view, and forming a fourth line and a fifth line over the first line, the second line, and the third line, the fourth line and the fifth line being orthogonal to the first line in the plan view. The method further includes etching a hole through the second line using the first line, the third line, the fourth line, and the fifth line as an etching mask, and filling the hole with a dielectric material to form a block.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Inventors: Eric Chih-Fang Liu, Shihsheng Chang, Kai-Hung Yu, Yun Han
  • Patent number: 11929319
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Publication number: 20240079558
    Abstract: A method of manufacturing a positive electrode material has the steps of synthesizing an iron metal in a phosphoric acid solution to form an iron phosphate dispersion solution; adding a vanadium pentoxide (V2O5), a non-ionic surfactant and a carbon source to the iron phosphate dispersion solution; and adding a lithium salt to the iron phosphate dispersion solution and then grinding and dispersing it to produce a positive electrode material. By regulating the timing of the addition of vanadium pentoxide (V2O5), the present invention enables the battery made of the positive electrode material to have the advantage of higher battery performance.
    Type: Application
    Filed: June 21, 2023
    Publication date: March 7, 2024
    Inventors: Chao-Nan Wei, Feng-Yen Tsai, Ya-Hui Wang, Han-Yu Chen
  • Publication number: 20240069619
    Abstract: A method, system, and article provide image processing with power reduction while using universal serial bus cameras.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Intel Corporation
    Inventors: Ko Han Wu, Thiam Wah Loh, Kenneth K. Lau, Wen-Kuang Yu, Ming-Jiun Chang, Andy Yeh, Wei Chih Chen
  • Patent number: 11915782
    Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Min Lee, Nam Hyung Kim, Dae Jeong Kim, Do Han Kim, Min Su Kim, Deok Ho Seo, Won Jae Shin, Yong Jun Yu, Il Gyu Jung, In Su Choi
  • Patent number: 11908685
    Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, where the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Ruei Jhan, Han-Yu Lin, Li-Te Lin, Pinyen Lin