Patents by Inventor Han Yu

Han Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055527
    Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
  • Patent number: 11898198
    Abstract: The disclosed embodiments concern methods, systems and computer program products for determining sequences of interest using unique molecular indexes (UMIs) that are uniquely associable with individual polynucleotide fragments, including sequences with low allele frequencies or long sequence length. In some implementations, the UMIs include variable-length nonrandom UMIs (vNRUMIs). Methods and systems for making and using sequencing adapters comprising vNRUMIs are also provided.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: February 13, 2024
    Assignee: Illumina, Inc.
    Inventors: Chen Zhao, Kevin Wu, Han-Yu Chuang, Jennifer Lococo, Alex So, Dwight Baker, Tatjana Singer
  • Publication number: 20240030281
    Abstract: A semiconductor device having a low-k isolation structure and a method for forming the same are provided. The semiconductor device includes channel structures, laterally extending on a substrate; gate structures, intersecting and covering the channel structures; and a channel isolation structure, laterally penetrating through at least one of the channel structures, and extending between separate sections of one of the gate structures along an extending direction of the one of the gate structures. A low-k dielectric material in the channel isolation structure comprises boron nitride.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Hua Chen, Cheng-Ming Lin, Han-Yu Lin, Wei-Yen Woon, Ming-Jie Huang, Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Szuya Liao
  • Publication number: 20240026348
    Abstract: Materials and methods for preparing nucleic acid libraries for next-generation sequencing are described herein. A variety of approaches are described relating to the use of unique molecular identifiers with transposon-based technology in the preparation of sequencing libraries. Also described herein are sequencing materials and methods for identifying and correcting amplification and sequencing errors.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 25, 2024
    Applicants: Illumina, Inc., Illumina Cambridge Limited
    Inventors: Susan C. Verity, Robert Scott Kuersten, Niall Anthony Gormley, Andrew B. Kennedy, Sarah E. Shultzaberger, Andrew Slatter, Emma Bell, Sebastien Georg Gabriel Ricoult, Grace DeSantis, Fiona Kaper, Han-Yu Chuang, Oliver Jon Miller, Jason Richard Betley, Stephen M. Gross, Mats Ekstrand
  • Publication number: 20240030317
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor fin over a semiconductor substrate; forming a gate structure over a first portion of the semiconductor fin; etching a source/drain recess over a second portion of the semiconductor fin; and performing an in-situ source/drain etching and epitaxy process to form a source/drain epitaxial structure in the second portion of the semiconductor fin. The step of performing the in-situ source/drain etching and epitaxy process comprises performing a dry etching process to adjust a profile of the source/drain recess in a chamber; and after adjusting the dry etching process, epitaxially growing the source/drain epitaxial structure in the source/drain recess in the chamber.
    Type: Application
    Filed: July 20, 2022
    Publication date: January 25, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Heng-Wen TING, Ming-Hua YU, Yee-Chia YEO, Han-Yu TANG
  • Publication number: 20240021019
    Abstract: An action detection method based on a human skeleton feature and a storage medium belong to the field of computer vision, and the method includes: for each person, extracting a series of body keypoints in every frame of the video as the human skeleton feature; calculating a body structure center point and approximating rigid motion area by using the human skeleton feature as a calculated value from the skeleton feature state, and predicting an estimated value in the next frame; performing target matching according to the estimated and calculated value, correlating the human skeleton feature belonging to the same target to obtain a skeleton feature sequence, and then correlating features of each keypoint in the temporal domain to obtain a spatial-temporal domain skeleton feature; inputting the skeleton feature into an action detection model to obtain an action category. In the disclosure, the accuracy of action detection is improved.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 18, 2024
    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Li Yu, Han Yu
  • Publication number: 20240011087
    Abstract: The disclosed embodiments concern methods, apparatus, systems and computer program products for determining sequences of interest using unique molecular index sequences that are uniquely associable with individual polynucleotide fragments, including sequences with low allele frequencies and long sequence length. In some implementations, the unique molecular index sequences include variable-length nonrandom sequences. In some implementations, the unique molecular index sequences are associated with the individual polynucleotide fragments based on alignment scores indicating similarity between the unique molecular index sequences and subsequences of sequence reads obtained from the individual polynucleotide fragments. System, apparatus, and computer program products are also provided for determining a sequence of interest implementing the methods disclosed.
    Type: Application
    Filed: August 3, 2023
    Publication date: January 11, 2024
    Inventors: Kevin Wu, Chen Zhao, Han-Yu Chuang, Alex So, Stephen Tanner, Stephen M. Gross
  • Patent number: 11871533
    Abstract: A carrier assembly for installing a hard disk drive (HDD) rapidly without tools or screws or other fasteners disk includes a bracket and a carrier. The carrier is movably disposed within the bracket. The hard disk drive is disposed with the carrier. The bracket includes a side plate and a plurality of first protrusions arranged on the side plate along with electrical connectors. The side plate defines interconnecting slots, a vertical first slot and a horizontal second slot. The carrier includes a lateral plate, a rotating handle connected to the lateral plate, and second protrusions arranged on the lateral plate. When the rotating handle is manually rotated, the second protrusion becomes locked within the first slot or the second slot to fix the HDD in place.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: January 9, 2024
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Ge Liu, Han-Yu Li, Bin-Bin Yang, Meng-Ya Cui
  • Publication number: 20240008373
    Abstract: In various embodiments, an improved structure for a PCM device is provided. The improved structure is configured to help prevent heat dissipation. In one example, the PCM device is an PCM RF Switch, which has a substrate, a heater, a dielectric/insulator layer, oxidation layers, electrodes, a PCM region, and/or any other components. The oxidation layers are configured to help prevent heat dissipation from the heater.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Chang-Chih Huang, Han-Yu Chen, Yu-Sheng Chen, Kuo-Chyuan Tzeng
  • Patent number: 11855192
    Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: December 26, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Han-Yu Lin, Fang-Wei Lee, Kai-Tak Lam, Raghunath Putikam, Tzer-Min Shen, Li-Te Lin, Pinyen Lin, Cheng-Tzu Yang, Tzu-Li Lee, Tze-Chung Lin
  • Patent number: 11849558
    Abstract: A server chassis includes a housing, a support frame, and a back plate. The housing includes a substrate. A fixing portion is vertically disposed on the substrate and is fixedly connected with the back plate. The support frame is fixedly connected with the substrate. A first protrusion is disposed on the support frame and is inserted into the back plate. The interior of the server chassis is rendered more compact, and the server chassis can accommodate eight hard disks. A server including the server chassis is also disclosed.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: December 19, 2023
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Yang Li, Han-Yu Li, Ya-Ni Zhang, Li Hou
  • Publication number: 20230403657
    Abstract: An OFDMA power control method includes: transmitting a first trigger frame to a station, wherein the first trigger frame includes a first target RSSI; receiving a first TB-PPDU from the station, wherein the first TB-PPDU is transmitted by the station using a first power according to the first target RSSI; measuring a first power of the first TB-PPDU to obtain a first measured RSSI; and generating a second the target RSSI according to the first measured RSSI.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 14, 2023
    Inventors: CHO-HAN YU, CHUN-KAI TSENG, WEN-YUNG LEE, JHE-YI LIN, SHAU-YU CHENG
  • Publication number: 20230397511
    Abstract: A dielectric isolation layer having a top surface may be formed over a substrate. A heater line, a phase change material (PCM) line, and an in-process conductive barrier plate may be formed over the dielectric isolation layer. An electrode material layer may be formed over the in-process conductive barrier plate. The electrode material layer and the in-process conductive barrier plate may be patterned such that patterned portions of the in-process conductive barrier plate include a first conductive barrier plate contacting a first area of a top surface of the PCM line, and a second conductive barrier plate contacting a second area of the top surface of the PCM line, and patterned portions of the electrode material layer include a first electrode contacting the first conductive barrier plate and a second electrode contacting the second conductive barrier plate.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Harry-Hak-Lay Chuang, Chia Wen Liang, Chang-Chih Huang, Han-Yu Chen, Kuo-Chyuan Tzeng, Tsung-Hao Yeh
  • Patent number: 11832448
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having sidewalls that define a recess within an upper surface of the semiconductor substrate. A plurality of upper electrode segments are arranged over the semiconductor substrate and are vertically separated from the upper surface of the semiconductor substrate by a first dielectric layer. A lower electrode segment is arranged directly between the sidewalls of the semiconductor substrate and directly between adjacent ones of the plurality of upper electrode segments. A second dielectric layer is arranged directly between the sidewalls of the semiconductor substrate and the lower electrode segment and also directly between the plurality of upper electrode segments and the lower electrode segment.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Chen Chen, Yu-Hsiung Wang, Han-Yu Chen
  • Patent number: 11830928
    Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Yu Lin, Chansyun David Yang, Tze-Chung Lin, Fang-Wei Lee, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11830948
    Abstract: A semiconductor device includes a semiconductor substrate, at least one semiconductor fin and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion and a first neck portion between the first portion and the second portion. A width of the first portion decreases as the first portion becomes closer to the first neck portion, and a width of the second portion increases as the second portion becomes closer to a bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
  • Publication number: 20230380096
    Abstract: A bracket assembly for a server to prevent tilting during transportation includes at least two cabinet columns and two brackets. The two brackets are spaced apart from each other. The at least two cabinet columns fixed on the two brackets. Each bracket includes a fixing portion, a supporting portion, and at least one protrusion. The supporting portion extends from an edge of the fixing portion toward the other bracket, the protrusion from the fixing portion is spaced apart from the supporting portion. The supporting portion and protrusion are disposed on a same side of the fixing portion. A bracket structure and server assembly includes the bracket assembly and a housing, each of two parallel sidewalls of the housing has a sliding groove to clamp the protrusions.
    Type: Application
    Filed: July 1, 2022
    Publication date: November 23, 2023
    Inventors: YANG LI, SAN-LONG ZHOU, HAN-YU LI, WEN-HU LU
  • Publication number: 20230377135
    Abstract: A system of automatically recognizing a malocclusion class is disclosed. The disclosure is to compute an occlusion grade based on an occlusion image, compute a lower teeth profile grade based on a lower teeth profile image, compute an upper teeth profile grade based on an upper teeth profile image, compute a side face profile grade based on a side face image, and determine a credibility of a malocclusion class based on the grades. A method and a computer program are also disclosed.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Inventors: Kio-Heng SAM, Cheng-Han YU
  • Patent number: D1011584
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: January 16, 2024
    Inventor: Chung Han Yu
  • Patent number: D1012344
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: January 23, 2024
    Inventor: Chung Han Yu