Patents by Inventor Hanan Weingarten

Hanan Weingarten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220209791
    Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicant: Kioxia Corporation
    Inventors: Avi Steiner, Amir Nassie, Anat Rot, Ofir Kanter, Hanan Weingarten
  • Publication number: 20220199183
    Abstract: Various implementations described herein relate to systems and methods for programming data, including determining a target row corresponding to a program command and setting row-based programming parameters for the target row using target physical device parameters of the target row and optimized programming parameters corresponding to the physical device parameters.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Applicant: Kioxia Corporation
    Inventors: Avi Steiner, Hanan Weingarten, Yasuhiko Kurosawa, Neil Buxton
  • Patent number: 11258466
    Abstract: A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate first soft information of the first codeword. The circuit may be further configured to generate second soft information of a second codeword. The circuit may be configured to generate third soft information based on the first soft information and the second soft information. The circuit may be configured to decode the result of the read operation on the flash memory using the third soft information.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: February 22, 2022
    Assignee: Kioxia Corporation
    Inventors: Ofir Kanter, Avi Steiner, Hanan Weingarten
  • Patent number: 11258464
    Abstract: Various implementations described herein relate to systems and methods for encoding and decoding data having input payload stored in a non-volatile storage device, including encoding the input payload by concatenating a plurality of short codewords to generate a plurality of encoded short codewords, and decoding the plurality of encoded short codewords to obtain the data, where each of the plurality of short codewords corresponding to a portion of the input payload.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: February 22, 2022
    Assignee: Kioxia Corporation
    Inventors: Avi Steiner, Hanan Weingarten
  • Patent number: 11183259
    Abstract: The present embodiments relate to methods for maintaining steady and high performance programming of non-volatile memory devices such as NAND-type flash devices. According to certain aspects, embodiments provide adaptive control of programming parameters over the lifespan of a NAND flash device so as to maintain write performance and obtain high endurance.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: November 23, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Avi Steiner, Hanan Weingarten, Yasuhiko Kurosawa
  • Patent number: 11082069
    Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining features for each of a plurality of component codes corresponding to the data by decoding each of the plurality of component codes, determining an extrinsic value output for each of the component codes based on the features, and after the extrinsic value output for each of the component codes is determined, decoding each of the plurality of component codes based on the extrinsic value outputs of all other component codes of the component codes. Each of the component codes depends on all other component codes.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: August 3, 2021
    Assignee: Kioxia Corporation
    Inventors: Avi Steiner, Hanan Weingarten
  • Patent number: 11024391
    Abstract: A flash memory system may include a flash memory and a circuit for performing operations of the flash memory. The circuit may be configured to estimate slope information of a plurality of threshold voltage samples based on a first read operation on the flash memory with a first reference voltage. The circuit may be configured to generate soft information based on the estimated slope information. The circuit may be configured to decode a result of a second read operation on the flash memory based on the soft information.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Avi Steiner, Hanan Weingarten
  • Patent number: 11016844
    Abstract: Various implementations described herein relate to systems and methods for encoding data having input bits to be stored in a non-volatile storage device, including mapping the input bits to a plurality of component codes of an error correction code (ECC) and encoding the input bits as the plurality of component codes, wherein first input bits of the input bits encoded by any of the plurality of component codes are encoded by every other component code of the plurality of component codes in a non-overlapping manner.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 25, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Avi Steiner, Hanan Weingarten, Meir Nadam-Olegnowicz, Ofir Kanter, Amir Nassie
  • Patent number: 10963338
    Abstract: A flash memory system may include a flash memory and a circuit for performing operations of the flash memory. The circuit may be configured to estimate slope information of a plurality of threshold voltage samples based on soft decoding errors in connection with a first read operation on the flash memory. The circuit may be further configured to generate estimated soft information based on the estimated slope information. The circuit may be further configured to decode a result of a second read operation on the flash memory based on the estimated soft information.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 30, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Avi Steiner, Hanan Weingarten
  • Publication number: 20200293400
    Abstract: Various implementations described herein relate to systems and methods for encoding data having input bits to be stored in a non-volatile storage device, including mapping the input bits to a plurality of component codes of an error correction code (ECC) and encoding the input bits as the plurality of component codes, wherein first input bits of the input bits encoded by any of the plurality of component codes are encoded by every other component code of the plurality of component codes in a non-overlapping manner.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Inventors: Avi Steiner, Hanan Weingarten, Meir Nadam-Olegnowicz, Ofir Kanter, Amir Nassie
  • Publication number: 20200293399
    Abstract: Various implementations described herein relate to systems and methods for performing error correction in a flash memory device by determining suggested corrections by decoding a codeword. In addition, whether a first set of the suggested corrections obtained based on a first component code of the plurality of component codes agree with a second set of the suggested corrections obtained based on a second component code of the plurality of component codes is determined. One of accepting the first set of the suggested corrections or rejecting the first set of the suggested corrections is selected based on whether the first set of the suggested corrections and the second set of the suggested corrections agree.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Inventors: Avi Steiner, Hanan Weingarten, Meir Nadam-Olegnowicz, Ofir Kanter, Amir Nassie
  • Publication number: 20200265910
    Abstract: The present embodiments relate to methods for maintaining steady and high performance programming of non-volatile memory devices such as NAND-type flash devices. According to certain aspects, embodiments provide adaptive control of programming parameters over the lifespan of a NAND flash device so as to maintain write performance and obtain high endurance.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: Kioxia Corporation
    Inventors: Avi STEINER, Hanan WEINGARTEN, Yasuhiko KUROSAWA
  • Patent number: 10658058
    Abstract: The present embodiments relate to methods for estimating bit error rates (BERs) associated with a flash memory. According to certain aspects, embodiments provide estimating the BER of multi-bit flash memories during the programming of the flash memory, and providing the estimated BER in a readable status register of the flash memory, thereby improving the speed of programming of the flash memory.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 19, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiko Kurosawa, Avi Steiner, Hanan Weingarten
  • Patent number: 10643730
    Abstract: The present embodiments relate to methods for maintaining steady and high performance programming of non-volatile memory devices such as NAND-type flash devices. According to certain aspects, embodiments provide adaptive control of programming parameters over the lifespan of a NAND flash device so as to maintain write performance and obtain high endurance.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: May 5, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Avi Steiner, Hanan Weingarten, Yasuhiko Kurosawa
  • Patent number: 10628255
    Abstract: A method for multi-dimensional decoding, the method may include receiving a multi-dimensional encoded codeword that comprises a payload and a redundancy section; wherein the payload comprises data and an error detection process signature; evaluating, during a multi-dimensional decoding process of the multi-dimensional encoded codeword, an hypothesis regarding a content of the payload; applying on the hypotheses an error detection process to provide an indication about a validity of the hypotheses; and proceeding with the multi-dimensional decoding process and finding a next hypothesis to be error detection process validated when the hypothesis is invalid.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: April 21, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Avi Steiner, Hanan Weingarten
  • Patent number: 10366770
    Abstract: The present embodiments relate to methods for estimating bit error rates (BERs) associated with a flash memory. According to certain aspects, embodiments provide estimating the BER of multi-bit flash memories during the programming of the flash memory, and providing the estimated BER in a readable status register of the flash memory, thereby improving the speed of programming of the flash memory.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: July 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiko Kurosawa, Avi Steiner, Hanan Weingarten
  • Patent number: 10305515
    Abstract: An encoder and a method for encoding a first stream of bits, the method may include splitting the first stream of bits to multiple second streams; encoding, in parallel and by using multiple linear feedback shift registers (LFSRs), the multiple second streams to provide third streams, wherein each second stream of the multiple second streams is encoded using an LFSR of the multiple LFSRs; wherein the encoding comprises feeding the multiple second streams to the multiple LFSRs; merging the third streams to provide a fourth stream; wherein the fourth stream is stored in the multiple LFSRs; and encoding the fourth stream to provide a fifth stream; wherein the encoding of the fourth stream comprises concatenating the multiple LFSRs while bypassing feedback circuits of some of the multiple LFSRs; and shifting the fourth stream through the multiple LFSRs.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: May 28, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Hanan Weingarten, Erez Sabbag, Amir Nassie
  • Patent number: 10120792
    Abstract: A method that includes sending to an embedded flash storage device (EFSD) and during a transaction, a data unit and recovery metadata that differs from a flash memory unit memory management data structure (FMUMMDS); instructing the EFSD to program the data unit and the recovery metadata to a group of flash memory cells; sending to the host computer a transaction completion indication in response to a successful completion of the programming and before a completion of a management process that comprises updating by the flash memory controller, the FMUMMDS to reflect (a) the recovery metadata and (b) physical address information related to the group of the flash memory cells; and programming, by the EFSD, the FMUMMDS to the flash memory unit; wherein the data structure is reconstructible based upon the recovery metadata and the physical address information related to the group of the flash memory cells.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: November 6, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Avigdor Segal, Hanan Weingarten, Igal Maly, Irena Shemesh
  • Patent number: 10079068
    Abstract: A system, a non-transitory computer readable medium and a method for wear estimation of a flash memory device, the method may include: programming information to a first portion of the flash memory device during a test programming process; measuring a duration of the test programming process; and estimating a wear characteristic of the first portion of the flash memory device thereby providing an estimated wear characteristic, wherein the estimating is responsive to the duration of the test programming process.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: September 18, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Hanan Weingarten, Avi Steiner
  • Patent number: 9954558
    Abstract: A method for fast decoding, the method may include (a) performing a hard read of a group of flash memory cells to provide hard read data; wherein the group of flash memory cells store a codeword that comprises component codes of multiple dimensions; (b) hard decoding the hard read data to provide a hard decoding result; wherein the hard decoding result comprises first suggested values of component codes of at least one dimension of the multiple dimensions; (c) performing at least one additional read attempt of the group of flash memory cells to provide additional data; (d) performing a partial extensiveness soft decoding the additional data, in response to the first suggested values, to provide a soft decoding result; and (e) wherein the soft decoding result comprises second suggested values of component codes of one or more dimensions of the multiple dimensions.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: April 24, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Avi Steiner, Avigdor Segal, Hanan Weingarten