Abstract: A method for programming data into a first plurality of rows within a second plurality of erase sectors of a flash memory device using a programming process having at least one selectable parameter, the method includes characterizing each of at least one row subsets, each row subset comprising at least one row from among said first plurality of rows, thereby to generate at least one row subset characteristic value; and programming data into at least a portion of at least one individual row belonging to at least one row subset, using a programming process having at least one selectable parameter, said at least one selectable parameter being set at least partly in accordance with the row subset characteristic value characterizing a row subset to which said individual row belongs; wherein at least two row subsets of an array of flash memory cells differ from each other by their row subset characteristic values.

Abstract: A low power Chien searching method employing Chien search circuitry comprising at least two hardware components that compute at least two corresponding bits comprising a Chien search output, the method comprising activating only a subset of the hardware components thereby to compute only a subset of the bits of the Chien search output; and activating hardware components other than those in the subset of hardware components, to compute additional bits of the Chien search output other than the bits in the subset of bits, only if a criterion on the subset of the bits of the Chien search output is satisfied.

Abstract: A system, method and computer readable medium for performing a first read attempt of multiple codeword portions while using a first read threshold candidate to provide multiple first read results, wherein the multiple codeword portions are stored in multiple flash memory cells; calculating a first read threshold candidate error correction decoding based score; wherein the calculating comprises error correction decoding of the multiple first read results; performing a second read attempt of the multiple codeword portions while using a second read threshold candidate to provide multiple second read results; calculating a second read threshold candidate error correction decoding based score; wherein the calculating comprises error correction decoding of the multiple second read results; and selecting a first read threshold out of the first and second read threshold candidates based on a relationship between the first and second read threshold candidate error correction decoding based scores.

Abstract: A method, system and a computer readable medium, the method may include programming multiple logical pages to a flash memory module according to a programming order; calculating a XOR value for each group of logical pages; storing the XOR value of each group of logical pages; and using a XOR value of a group of logical pages to reconstruct a corrupted logical page of the group of logical pages; wherein up to a single logical page of each group of logical pages is programmed to a each row of a flash memory die; and wherein logical page numbers of logical pages of a same type that belong to different groups of logical pages belong to non-overlapping numerical ranges.

Abstract: A system and method for merging sectors of a flash memory module, the method includes: receiving multiple sectors, each received sector is associated with a current erase block out of multiple (L) erase blocks; accumulating the received sectors in a sector buffer, the sector buffer is stored in a non-volatile memory module; maintaining a merged sector map indicative of a sectors of the sector buffer that have been merged and sectors of the sector buffer waiting to be merged; finding a first sector waiting to be merged according to the merged sector map; merging the first sector and other sectors that belong to a same erase block as the first sector; and updating the merged sector map to indicate that that the first second and the other sectors that belonged to the same erase block were merged.

Abstract: A system and method are provided for data recovery in a multi-level cell memory device. One or more bits may be programmed sequentially in one or more respective levels of multi-level cells in the memory device. An interruption of programming a subsequent bit in a subsequent second or greater level of the multi-level cells may be detected. Data may be recovered from the multi-level cells defining the one or more bits programmed preceding the programming interruption of the second or greater level.

Abstract: A system and method for analog encryption and decryption. A threshold level encryption key stream is generated and a programming level for each bit of a cipher data stream, with each bit having a one or zero state, is determined, where a threshold for distinguishing between the one or zero state for each bit varies based on a corresponding entry in the threshold level encryption key steam. Each bit of the cipher data stream in a cell of a memory is programmed based on the programming level.

Abstract: A non-transitory computer readable medium, a flash controller and a method for state responsive encoding and programming; the method may include encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells; and programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state, the state being either an estimated state or an actual state.

Abstract: A system and method for adjusting read threshold voltage values, for example, in a read circuit internal to a memory device. The quality of an associated read result may be estimated for each read threshold voltage value used to read memory cells. Only read results estimated to have sufficient quality may be allowed to pass to storage. The read threshold voltage value may be adjusted for subsequent read operations, for example, if the associated read result is estimated to have insufficient quality. The read threshold voltage value may be iteratively adjusted, for example, until a read result is estimated to have sufficient quality.

Abstract: A method, system and computer-readable medium are provided for reading information from a memory unit. A request may be received to read information from a set of memory cells in the memory unit. At least one read threshold in an initial set of read thresholds may be perturbed to generate a perturbed set of read thresholds. The set of memory cells may be read using the perturbed set of read thresholds to provide a read result. The performance of said reading may be evaluated using the perturbed set of read thresholds. The at least one read threshold may be iteratively perturbed for each sequential read operation that the read performance is evaluated to be sub-optimal.

Abstract: A method and an apparatus that has Chien search capabilities, the apparatus includes a first hardware circuit and a second hardware circuit. The first hardware circuit evaluates an error locator polynomial for a first element of a finite field over which the error locator polynomial is defined to provide a first set of intermediate results and a first Chien search result and provides the first set of intermediate results to the second hardware circuit; the second hardware circuit evaluates the error locator polynomial for a second element of the finite field to provide a second Chien search result in response to the first set of intermediate results. The first hardware circuit may be substantially bigger than the second hardware circuit and the first element may differ from the second element.

Abstract: A system and method for encoding information arriving from a host in order to store the coded information in flash memory, the method comprising encoding information arriving from a host for storage at a flash memory location including generating a number of redundancy bytes, the encoding proceeding at an encoding rate which is a function of the number of redundancy bytes generated, the encoding including determining an effective error rate, including an anticipated rate of expected reading errors, for the flash memory location; and selecting the encoding rate as a function of the effective error rate such that the number of redundancy bytes is sufficient to overcome the anticipated rate of expected reading errors with a predetermined degree of certainty.

Abstract: A method for decoding a plurality of flash memory cells which are error correction-coded, the method may include: comparing physical values residing in the plurality of flash memory cells to a first set of decision thresholds thereby to provide a first item of comparison information for each of the plurality of cells; comparing physical values residing the plurality of flash memory cells to a second set of decision thresholds, thereby to provide a second item of comparison information for each of the plurality of cells, wherein neither of the first and second sets of decision thresholds is a subset of the other; and determining logical values for the plurality of flash memory cells by combining said first and second items of comparison information.

Abstract: A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

Abstract: A method for converting a measured physical level of a cell into a logical value, in an array of memory cells storing physical levels which diminish over time, the method may include: determining extent of deterioration of the physical levels and determining thresholds accordingly for at least an individual cell in the array; and reading the individual cell including reading a physical level in said cell and converting said physical level into a logical value using at least some of said thresholds, wherein said determining extent of deterioration comprises storing predefined physical levels rather than data-determined physical levels in each of a plurality of cells and determining extent of deterioration by computing deterioration of said predefined physical levels.

Abstract: A flash memory system comprising temporary memory, writing apparatus for writing first logical data from the temporary memory into flash memory cells having at least two levels, thereby to generate a physical representation of the first logical data including known errors, reading apparatus for reading the physical representation from the cells, thereby to generate, and store in the temporary memory, second logical data which if read immediately is identical to the first logical data other than the known errors; and controlling apparatus controlling the writing apparatus and the reading apparatus and including known error ID apparatus operative to identify the known errors by comparing the first logical data to second logical data read immediately after the physical representation is generated, to store information characterizing the known errors and to use the information, when the second logical data is next read, to correct the known errors.

Abstract: Apparatus and methods for operating a flash device characterized by use of Lee distance based codes in a flash device so as to increase the number of errors that can be corrected for a given number of redundancy cells, compared with Hamming distance based codes.

Abstract: A system and method for soft decoding data. A plurality of candidate error corrections may be generated to correct one or more data bits having soft bit information. Each candidate error correction may define suggested changes to the data bits and is associated with a soft bit value. The soft bit values associated the plurality of candidate error corrections may be mapped to a uniform scale, for example, a uniform finite or integer grid. The plurality of candidate error corrections may be ordered to have combined associated mapped values in a monotonically non-decreasing order. One or more of the plurality of candidate error corrections may be soft decoded in the order of the associated mapped values by a decoding operation for each candidate error correction therein with the associated non-mapped soft bit values.

Abstract: Flash memory apparatus including a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain portions from among said plurality of memory portions including allocating data, during the first duration of time, only to the certain portions, thereby to define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for the first duration of time.

Abstract: A method for decoding a plurality of flash memory cells which are error-correction-coded as a unit, the method comprising providing a hard-decoding success indication indicating whether or not hard-decoding is at least likely to be successful; and soft-decoding the plurality of flash memory cells at a first resolution only if the hard-decoding success indication indicates that the hard-decoding is not at least likely to be successful.