Abstract: A flash memory system may include a flash memory and a circuit for performing operations of the flash memory. The circuit may be configured to estimate slope information of a plurality of threshold voltage samples based on soft decoding errors in connection with a first read operation on the flash memory. The circuit may be further configured to generate estimated soft information based on the estimated slope information. The circuit may be further configured to decode a result of a second read operation on the flash memory based on the estimated soft information.

Abstract: Various implementations described herein relate to systems and methods for performing error correction in a flash memory device by determining suggested corrections by decoding a codeword. In addition, whether a first set of the suggested corrections obtained based on a first component code of the plurality of component codes agree with a second set of the suggested corrections obtained based on a second component code of the plurality of component codes is determined. One of accepting the first set of the suggested corrections or rejecting the first set of the suggested corrections is selected based on whether the first set of the suggested corrections and the second set of the suggested corrections agree.

Abstract: Various implementations described herein relate to systems and methods for encoding data having input bits to be stored in a non-volatile storage device, including mapping the input bits to a plurality of component codes of an error correction code (ECC) and encoding the input bits as the plurality of component codes, wherein first input bits of the input bits encoded by any of the plurality of component codes are encoded by every other component code of the plurality of component codes in a non-overlapping manner.

Abstract: The present embodiments relate to methods for maintaining steady and high performance programming of non-volatile memory devices such as NAND-type flash devices. According to certain aspects, embodiments provide adaptive control of programming parameters over the lifespan of a NAND flash device so as to maintain write performance and obtain high endurance.

Abstract: The present embodiments relate to methods for estimating bit error rates (BERs) associated with a flash memory. According to certain aspects, embodiments provide estimating the BER of multi-bit flash memories during the programming of the flash memory, and providing the estimated BER in a readable status register of the flash memory, thereby improving the speed of programming of the flash memory.

Abstract: The present embodiments relate to methods for maintaining steady and high performance programming of non-volatile memory devices such as NAND-type flash devices. According to certain aspects, embodiments provide adaptive control of programming parameters over the lifespan of a NAND flash device so as to maintain write performance and obtain high endurance.

Abstract: A method for multi-dimensional decoding, the method may include receiving a multi-dimensional encoded codeword that comprises a payload and a redundancy section; wherein the payload comprises data and an error detection process signature; evaluating, during a multi-dimensional decoding process of the multi-dimensional encoded codeword, an hypothesis regarding a content of the payload; applying on the hypotheses an error detection process to provide an indication about a validity of the hypotheses; and proceeding with the multi-dimensional decoding process and finding a next hypothesis to be error detection process validated when the hypothesis is invalid.

Abstract: The present embodiments relate to methods for estimating bit error rates (BERs) associated with a flash memory. According to certain aspects, embodiments provide estimating the BER of multi-bit flash memories during the programming of the flash memory, and providing the estimated BER in a readable status register of the flash memory, thereby improving the speed of programming of the flash memory.

Abstract: An encoder and a method for encoding a first stream of bits, the method may include splitting the first stream of bits to multiple second streams; encoding, in parallel and by using multiple linear feedback shift registers (LFSRs), the multiple second streams to provide third streams, wherein each second stream of the multiple second streams is encoded using an LFSR of the multiple LFSRs; wherein the encoding comprises feeding the multiple second streams to the multiple LFSRs; merging the third streams to provide a fourth stream; wherein the fourth stream is stored in the multiple LFSRs; and encoding the fourth stream to provide a fifth stream; wherein the encoding of the fourth stream comprises concatenating the multiple LFSRs while bypassing feedback circuits of some of the multiple LFSRs; and shifting the fourth stream through the multiple LFSRs.

Abstract: A method that includes sending to an embedded flash storage device (EFSD) and during a transaction, a data unit and recovery metadata that differs from a flash memory unit memory management data structure (FMUMMDS); instructing the EFSD to program the data unit and the recovery metadata to a group of flash memory cells; sending to the host computer a transaction completion indication in response to a successful completion of the programming and before a completion of a management process that comprises updating by the flash memory controller, the FMUMMDS to reflect (a) the recovery metadata and (b) physical address information related to the group of the flash memory cells; and programming, by the EFSD, the FMUMMDS to the flash memory unit; wherein the data structure is reconstructible based upon the recovery metadata and the physical address information related to the group of the flash memory cells.

Abstract: A system, a non-transitory computer readable medium and a method for wear estimation of a flash memory device, the method may include: programming information to a first portion of the flash memory device during a test programming process; measuring a duration of the test programming process; and estimating a wear characteristic of the first portion of the flash memory device thereby providing an estimated wear characteristic, wherein the estimating is responsive to the duration of the test programming process.

Abstract: A method for fast decoding, the method may include (a) performing a hard read of a group of flash memory cells to provide hard read data; wherein the group of flash memory cells store a codeword that comprises component codes of multiple dimensions; (b) hard decoding the hard read data to provide a hard decoding result; wherein the hard decoding result comprises first suggested values of component codes of at least one dimension of the multiple dimensions; (c) performing at least one additional read attempt of the group of flash memory cells to provide additional data; (d) performing a partial extensiveness soft decoding the additional data, in response to the first suggested values, to provide a soft decoding result; and (e) wherein the soft decoding result comprises second suggested values of component codes of one or more dimensions of the multiple dimensions.

Abstract: A computer readable medium, a system and a method for flash memory device that my store instructions for receiving from a host computer a first command that is a write command of a first data unit to a flash memory device, receiving, from the host computer, a second command that is indicative of a manner in which at least one entity out of (a) memory management metadata, (b) the first data unit and (c) at least one other data unit, should be stored in the flash memory device, and programming the at least one entity in the flash memory device in response to the second command.

Abstract: According to an embodiment of the invention there may be provided a non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to sample a flash memory cell that belongs to a die, by attempting, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value; sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples; defining a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell; and determining, by a processor that belongs to the die, a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample. The processor may belong to the sampling circuit or may not belong to the sampling circuit.

Abstract: A method for interleaved multi-dimensional encoding, the method may include receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the group of bits; and encoding the first and second versions of the groups of bits in an interleaved manner; wherein the encoding comprises calculating at least one codeword component of the first version by encoding a set of bits of the first version and at least a portion of a redundancy of at least one data entity of the second version and calculating at least one codeword component of the second version by encoding a set of bits of the second version and at least a portion of a redundancy of at least one data entity of the first version.

Abstract: A method for error correction, the method comprises receiving a codeword that comprises a payload and a redundancy section; error-correction decoding the codeword by applying a syndrome-based error correction process to provide an amended payload and an error-correction decoding success indicator; wherein the amended payload comprises an amended CRC signature and an amended payload data; calculating, using the amended payload CRC signature, a validity of the amended payload to provide a CRC validity result; estimating a number of errors in the redundancy section; and determining that the error-correction succeeded when the number of errors in the redundancy section did not exceed a threshold, the error correction success indicator indicates that the error-correction decoding failed, and the CRC validity result indicates that the amended payload is valid.

Abstract: A method for multilevel programming flash memory cells of a three dimensional array of flash memory cells, the method may include receiving or determining a multiple phase programming scheme that is responsive to coupling between flash memory cells of the three dimensional array; and programming data to multiple flash memory cells of the three dimensional array in response to the multiple phase programming scheme. The multiple phase programming scheme determine a manner in which multiple programming levels are applied. At least two programming levels of the multiple programming levels correspond to bits of different significance.

Abstract: A method for wear reduction of a flash memory module, the method may include reading data stored in a group of flash memory cells to provide a read data; wherein the reading comprise supplying a bias voltage that is lower than a write bias voltage; wherein the write bias voltage was supplied to the group of flash memory cells during a writing of the data to the group of flash memory cells; and decoding the read data, by applying a decoding process of a given complexity, to provide decoded data.

Abstract: A method for managing an encoding process, the method includes receiving or determining, by a processor, (i) code rates for multiple pages, and (ii) sizes of a plurality of data segments to be stored in the multiple pages after being encoded to provide multiple codewords; determining, by the processor, sizes of the multiple codewords while maintaining the code rates for the multiple pages and minimizing a number of split data segments out of the plurality of data segments, wherein each split data segment is split between at least two codewords of the multiple codewords, wherein a retrieval of the split data segment involves a retrieval of the at least two codewords; and sending to an encoder information about the sizes of the multiple codewords.

Abstract: A method of managing a non-volatile memory device, the method comprising receiving data sectors; wherein each data sector belongs to a memory space subset out of multiple memory space subsets; wherein the multiple memory space subsets comprise a plurality of logical memory blocks; wherein the memory space is partitioned to the multiple memory space subsets based upon expected or monitored memory access patterns; writing each data sector into a data block that is allocated to a memory space subset that is associated with the data sector; wherein the data block belongs to a buffer of the non-volatile memory device; maintaining a management data structure that comprises location metadata about a location of each data sector in the buffer; and merging, if a criterion is fulfilled and before the buffer becomes full, data sectors stored at different data blocks and belong to a same set of logical memory blocks into a sequential portion of the non-volatile memory device, wherein the sequential portion differs from t