Patents by Inventor Hang-Ting Lue

Hang-Ting Lue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200098774
    Abstract: A memory device comprises a stack of conductive strips separated by insulating strips, the conductive strips in the stack extending in a first direction. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through the conductive strips in the stack, each of the hemi-cylindrical vertical channel structures having a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures on the sidewalls of the conductive strips. The hemi-cylindrical vertical channel structures comprise semiconductor films having outside surfaces in contact with the data storage structures on the sidewalls of the conductive strips.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue
  • Patent number: 10566348
    Abstract: A memory device comprises a reference conductor, and a stack of conductive strips separated by insulating strips, where the conductive strips in the stack extend in a first direction, and the stack is disposed on the reference conductor. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through respective vias in the conductive strips in the stack, and comprising semiconductor films in electrical contact with the reference conductor having outside surfaces. Each of the hemi-cylindrical vertical channel structures has a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures between the outside surfaces of the semiconductor films and sidewalls of the vias in the conductive strips.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: February 18, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue
  • Publication number: 20200026990
    Abstract: A neural network system for execution of a sum-of-products operation includes a memory device and a controller. The memory device includes a 3D array having a plurality of memory cells with programmable conductances disposed in cross-points of a plurality of cell body lines and gate lines, a gate driver coupled to the gate lines and applying control gate voltages in combination with the programmable conductances for corresponding to weights of terms in the sum-of-products operation, a input driver used to apply voltages to the memory cells corresponding to input variables, a plurality of input lines connecting the cell body lines to the input driver, a sensing circuit used to sense currents passing through the memory cells corresponding the terms in the sum-of-products operation, a buffer circuit used to store the terms. The controller is used to control the memory device summing up the terms in the sum-of-products operation.
    Type: Application
    Filed: October 29, 2018
    Publication date: January 23, 2020
    Inventor: Hang-Ting LUE
  • Patent number: 10535673
    Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: January 14, 2020
    Assignee: Macronix International Co., Ltd.
    Inventors: Teng-Hao Yeh, Chih-Wei Hu, Hang-Ting Lue
  • Publication number: 20190371804
    Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 5, 2019
    Applicant: Macronix International Co., Ltd.
    Inventors: Teng-Hao Yeh, Chih-Wei Hu, Hang-Ting Lue
  • Patent number: 10403637
    Abstract: A memory device includes a plurality of stacks of conductive strips alternating with insulating strips, the insulating strips having first and second sides, and the conductive strips having first sidewalls recessed relative to the first sides of the insulating strips which define first recessed regions in sides of the stacks. Vertical channel pillars are disposed between the stacks, the vertical channel pillars having first and second channel films disposed on adjacent stacks and a dielectric material between and contacting the first and second channel films. Data storage structures at cross points of the vertical channel pillars and the conductive strips include tunneling layers in contact with the vertical channel pillars, discrete charge trapping elements in the first recessed regions in contact with the tunneling layers and blocking layers between the discrete charge trapping elements and the first sidewalls of the conductive strips.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: September 3, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Patent number: 10388720
    Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: August 20, 2019
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Teng-Hao Yeh
  • Patent number: 10381094
    Abstract: A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i?1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i?1).
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: August 13, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chen-Jun Wu, Chih-Chang Hsieh, Tzu-Hsuan Hsu, Hang-Ting Lue
  • Publication number: 20190156901
    Abstract: A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.
    Type: Application
    Filed: November 20, 2017
    Publication date: May 23, 2019
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Chen Chen, Hang-Ting Lue
  • Publication number: 20190148393
    Abstract: A device comprises a 3D array of cells arranged for execution of a sum-of-products operation, the cells in the 3D array disposed in cross-points of a plurality of vertical lines and a plurality of horizontal lines, the cells having programmable conductances. A gate driver is coupled to gate lines which applies control gate voltages which in combination with the programmable conductances of the cells correspond to weights Wxyz of terms in the sum-of-products operation. An input driver applies voltages to cells in the array corresponding to input variables Xy. A sensing circuit senses a sum of currents from cells in the 3D array corresponding to the sum-of-products.
    Type: Application
    Filed: July 17, 2018
    Publication date: May 16, 2019
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Patent number: 10276250
    Abstract: A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 30, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Chen Chen, Hang-Ting Lue
  • Patent number: 10211218
    Abstract: A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films connected at the bottom of the trench between the stacks, and have outside surfaces and inside surfaces. The outside surfaces contact the data storage structures on the sidewalls of the corresponding even and odd stacks forming a 3D array of memory cells; the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films having a U-shaped current path.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: February 19, 2019
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • Patent number: 10141328
    Abstract: A 3D memory device includes a substrate, a ridge-shaped stack, a memory layer, a channel layer and a capping layer. The ridge-shaped stack includes a plurality of conductive strips extending along a first direction and stacked on the substrate. The memory layer is stacked on a vertical sidewall of the ridge-shaped stack along a second direction that forms a non-straight with the first direction. The channel layer is stacked on the memory layer along the second direction and has a narrow sidewall having a long side extending along the first direction. The capping layer is stacked on the narrow sidewall along a third direction that forms a non-straight angle with the second direction.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: November 27, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hang-Ting Lue, Wei-Chen Chen
  • Publication number: 20180211969
    Abstract: A memory device includes a plurality of stacks of conductive strips alternating with insulating strips, the insulating strips having first and second sides, and the conductive strips having first sidewalls recessed relative to the first sides of the insulating strips which define first recessed regions in sides of the stacks. Vertical channel pillars are disposed between the stacks, the vertical channel pillars having first and second channel films disposed on adjacent stacks and a dielectric material between and contacting the first and second channel films. Data storage structures at cross points of the vertical channel pillars and the conductive strips include tunneling layers in contact with the vertical channel pillars, discrete charge trapping elements in the first recessed regions in contact with the tunneling layers and blocking layers between the discrete charge trapping elements and the first sidewalls of the conductive strips.
    Type: Application
    Filed: January 20, 2017
    Publication date: July 26, 2018
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: HANG-TING LUE
  • Publication number: 20180175051
    Abstract: A 3D memory device includes a substrate, a ridge-shaped stack, a memory layer, a channel layer and a capping layer. The ridge-shaped stack includes a plurality of conductive strips extending along a first direction and stacked on the substrate. The memory layer is stacked on a vertical sidewall of the ridge-shaped stack along a second direction that forms a non-straight with the first direction. The channel layer is stacked on the memory layer along the second direction and has a narrow sidewall having a long side extending along the first direction. The capping layer is stacked on the narrow sidewall along a third direction that forms a non-straight angle with the second direction.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 21, 2018
    Inventors: Hang-Ting Lue, Wei-Chen Chen
  • Publication number: 20180102177
    Abstract: A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i?1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i?1).
    Type: Application
    Filed: October 11, 2016
    Publication date: April 12, 2018
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chen-Jun WU, Chih-Chang Hsieh, Tzu-Hsuan Hsu, Hang-Ting LUE
  • Patent number: 9922989
    Abstract: A memory device is provided. The memory device includes a bottom conductive line, a stacked structure, a side oxide layer, a dielectric layer and a side semiconductor layer. The stacked structure is disposed on the bottom conductive line, and includes a first semiconductor layer, a second semiconductor layer disposed above the first semiconductor layer, and a plurality of oxide layers alternately stacked with the first semiconductor layer and the second semiconductor layer. The side oxide layer is disposed on both side walls of the first conductive layer. The dielectric layer is disposed on the stacked structure. The side semiconductor layer is disposed on the dielectric layer.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: March 20, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Publication number: 20180053772
    Abstract: A memory device is provided. The memory device includes a bottom conductive line, a stacked structure, a side oxide layer, a dielectric layer and a side semiconductor layer. The stacked structure is disposed on the bottom conductive line, and includes a first semiconductor layer, a second semiconductor layer disposed above the first semiconductor layer, and a plurality of oxide layers alternately stacked with the first semiconductor layer and the second semiconductor layer. The side oxide layer is disposed on both side walls of the first conductive layer. The dielectric layer is disposed on the stacked structure. The side semiconductor layer is disposed on the dielectric layer.
    Type: Application
    Filed: October 11, 2016
    Publication date: February 22, 2018
    Inventor: Hang-Ting Lue
  • Patent number: 9831257
    Abstract: A memory device is provided that includes a plurality of memory cells. The memory device includes a plurality of stacks of conductive strips separated by insulating strips. Data storage structures including floating gates are disposed along the conductive strips in the stacks. Vertical channel films are disposed on sidewalls of the stacks. Memory cells in the plurality of memory cells have channels in the vertical channel films, and control gates in the conductive strips. A tunnel oxide layer is disposed between the vertical channel films and the floating gates. The floating gates can be coplanar with conductive strips in the plurality of stacks, or be disposed between the conductive strips in the plurality of stacks.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: November 28, 2017
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • Patent number: RE47311
    Abstract: Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: March 19, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hang-Ting Lue, Erh-Kun Lai