Abstract: A memory device and an operation method thereof are provided. The operation method comprises: in performing a multiply accumulate (MAC) operation, inputting a plurality of inputs into a plurality of memory cells via a plurality of first signal lines; outputting a plurality of cell currents from the memory cells to a plurality of second signal lines based on a plurality of weights of the memory cells; summing the cell currents on each of the second signal lines into a plurality of signal line currents: summing the signal line currents into a global signal line current: and converting the global signal line current into an output, wherein the output represents a MAC operation result of the inputs and the weights.

Abstract: A three-dimension (3D) memory device and an operation method thereof are provided. The 3D memory device includes: a memory array including a plurality of memory cells; a controller coupled to the memory array; and a match circuit coupled to memory array, wherein in data search and match, the controller selects from the memory cells a plurality of target memory cells sharing a same target global signal line, and the controller selects a plurality of target word lines sharing the target global signal line as a plurality of target search lines, wherein a search data sends to the target memory cells via the target search lines for data matching; the target global signal line is precharged; and outputting a match address based on whether a voltage on the target global signal line is pulled down or not.

Abstract: A three-dimension (3D) memory device and an operation method thereof are provided. The 3D memory device includes: a memory array including a plurality of memory cells; a controller coupled to the memory array; and a match circuit coupled to memory array, wherein in data search and match, the controller selects from the memory cells a plurality of target memory cells sharing a same target global signal line, and the controller selects a plurality of target word lines sharing the target global signal line as a plurality of target search lines, wherein a search data sends to the target memory cells via the target search lines for data matching; the target global signal line is precharged; and outputting a match address based on whether a voltage on the target global signal line is pulled down or not.

Abstract: A memory device includes a source element, a drain element, channel layers, control electrode layers, and a memory layer. The channel layers are individually electrically connected between the source element and the drain element. Memory cells are defined in the memory layer between the control electrode layers and the channel layers.

Abstract: A semiconductor device includes a substrate, a stack, a conductive pillar, a memory layer, and a salicide layer. The stack is disposed on the substrate, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers that are alternately stacked along a first direction. The conductive pillar penetrates the stack along the first direction. The memory layer surrounds the conductive pillar. The salicide layer surrounds the conductive pillar, wherein the memory layer is disposed between the conductive pillar and the salicide layer.

Abstract: A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor.

Abstract: The present disclosure provides a three-dimensional memory device and a method for manufacturing the same. The three-dimensional memory device includes a plurality of tiles, and each tiles includes a plurality of blocks, and each blocks includes a gate stacked structure, a conductive layer, first ring-shaped channel pillars, source/drain pillars, and charge storage structures. The gate stacked structure is disposed on the substrate and includes gate layers electrically insulated from each other. The conductive layer is disposed between the substrate and the gate stacked structure. The first ring-shaped channel pillars are disposed on the substrate and located in the gate stacked structure. The source/drain pillars are disposed on the substrate, and each of the first ring-shaped channel pillars are configured with two source/drain pillars disposed therein. Each of the charge storage structures is disposed between the corresponding gate layer and the corresponding first ring-shaped channel pillar.

Abstract: Provided is a memory device including a substrate, a stack structure, a polysilicon layer, a vertical channel structure, and a charge storage structure. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The polysilicon layer is disposed between the substrate and the stack structure. The vertical channel structure penetrates through the stack structure and the polysilicon layer. The charge storage structure is at least disposed between the vertical channel structure and the plurality of conductive layers.

Abstract: Provided is a flash memory includes a gate stack structure, a channel pillar, a first conductive pillar, a second conductive pillar, and a gate dielectric layer. The gate stack structure includes a plurality of gate layers electrically insulated from each other. Each gate layer includes a ferroelectric portion disposed between a sidewall of a first portion and a sidewall of a second gate portion. A thickness of the second gate portion is smaller than a thickness of the first gate portion. A channel pillar penetrates the gate stack structure. The first and second conductive pillars are disposed in the channel pillar. The first and second conductive pillars are separated from each other, and are each connected to the channel pillar. The gate dielectric layer is disposed between another sidewall of the first gate portion and the channel pillar.

Abstract: An in-memory computing device including a plurality of memory cell arrays and a plurality of sensing amplifiers are provided. The memory cell arrays respectively receive a plurality of input signals. The input signals are divided into a plurality of groups. The groups respectively have at least one partial input signal. The at least one partial input signal of each of the groups has a same value. Numbers of the at least one partial input signal in the groups sequentially form a geometric sequence with a common ration equal to 2. The memory cell arrays respectively provide a plurality of weightings, and perform multiply-add operations respectively according to the received input signals and the weightings to generate a plurality of computation results. The sensing amplifiers respectively generate a plurality of sensing results according to the computation results.

Abstract: A semiconductor device includes a substrate, a stack, a conductive pillar, a memory layer, and a salicide layer. The stack is disposed on the substrate, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers that are alternately stacked along a first direction. The conductive pillar penetrates the stack along the first direction. The memory layer surrounds the conductive pillar. The salicide layer surrounds the conductive pillar, wherein the memory layer is disposed between the conductive pillar and the salicide layer.

Abstract: A memory structure is provided. The memory structure includes a first channel body, a first source region, a first drain region, a first gate structure and a second gate structure. The first source region has a first conductivity and connects to a first end of the first channel body. The first drain region has a second conductivity and connects to a second end of the first channel body separated from the first end. The first gate structure is disposed adjacent to the first channel body and between the first end and the second end. The second gate structure disposed adjacent to the first channel body and between the first end and the second end.

Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

Abstract: Provided is an operation method for a memory device, the operation method comprising: performing an erase operation; performing a verify-read operation on a memory cell to generate a cell current, the memory cell including a first transistor and a second transistor; checking whether the cell current is lower than a first cell current threshold; when the cell current is not lower than the first cell current threshold, increasing a memory gate voltage until the cell current is lower than the first cell current threshold, wherein the memory gate voltage is applied to the first transistor; fixing the memory gate voltage and increasing a drain voltage; checking whether the cell current is lower than a second cell current threshold; and if the cell current is not lower than the second cell current threshold, increasing the drain voltage until the cell current is lower than the second cell current threshold.

Abstract: A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor.

Abstract: Provided is an operation method for a memory device, the operation method comprising: performing an erase operation; performing a verify-read operation on a memory cell to generate a cell current, the memory cell including a first transistor and a second transistor; checking whether the cell current is lower than a first cell current threshold; when the cell current is not lower than the first cell current threshold, increasing a memory gate voltage until the cell current is lower than the first cell current threshold, wherein the memory gate voltage is applied to the first transistor; fixing the memory gate voltage and increasing a drain voltage; checking whether the cell current is lower than a second cell current threshold; and if the cell current is not lower than the second cell current threshold, increasing the drain voltage until the cell current is lower than the second cell current threshold.

Abstract: Provided are various three-dimensional flash memory devices. A three-dimensional flash memory device includes a gate stacked structure, separate arc-shaped channel pillars, source/drain pillars and a charge storage structure. The gate stacked structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. The arc-shaped channel pillar are disposed on the substrate and located in the gate stacked structure. The source/drain pillars are disposed on the substrate and penetrate through the gate stacked structure, wherein two source/drain pillars are disposed at two ends of each of the arc-shaped channel pillars. The charge storage structure is disposed between each of the plurality of gate layers and the corresponding arc-shaped channel pillar.

Abstract: An in-memory computation device including a memory array, p×q analog to digital converters (ADCs) and a ladder adder is provided. The memory array is divided into p×q memory tiles, where p and q are positive integers larger than 1. Each of the memory tiles has a plurality local bit lines coupled to a global bit line respectively through a plurality of bit line selection switches. The bit line selection switches are turned on or cur off according to a plurality of control signals. The memory array receives a plurality of input signals. The ADCs are respectively coupled to a plurality of global bit lines of the memory tiles. The ADCs respectively convert electrical signals on the global bit lines to generate a plurality of sub-output signals. The ladder adder is coupled to the ADCs, and performs an addition operation on the sub-output signals to generate a calculation result.

Abstract: A semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a first staircase structure, a second staircase structure, a conductive pillar, and a contact pillar. The first staircase structure includes conductive stair layers. The conductive pillar passes through the second staircase structure. The conductive pillar has an upper conductive pillar end and a lower conductive pillar end opposing to the upper conductive pillar end. The contact pillar is electrically connected on one conductive stair layer of the conductive stair layers. The contact pillar has an upper contact end and a lower contact end opposing to the upper contact end. The upper contact end and the lower contact end are respectively electrically connected to the upper conductive pillar end of the conductive pillar and the one conductive stair layer.

Abstract: A 3D flash memory is provided to includes a gate stack structure comprising a plurality of gate layers electrically insulated from each other, a cylindrical channel pillar vertically extending through each gate layer of the gate stack structure, a first conductive pillar vertically extending through the gate stack structure, the first conductive pillar being located within the cylindrical channel pillar and being electrically connected to the cylindrical channel pillar, and a second conductive pillar extending through the gate stack structure, the second conductive pillar being located within the cylindrical channel pillar and being electrically connected to the cylindrical channel pillar, the first conductive pillar and the second conductive pillar being separated from each other. The 3D flash memory also includes a ferroelectric layer disposed between gate layers of the gate stack structure and the cylindrical channel pillar.