Abstract: A memory apparatus and compensation method for a computation result thereof are provided. The memory apparatus includes a memory sub-block, a reference memory sub-block and a control circuit. During a computation phase, the memory sub-block receives an input signal, and generates a computation result by a multiply-accumulate operation according to the input signal. The reference memory sub-block includes a plurality of memory cells pre-programmed with a reference weight value. The reference memory sub-block receives a reference input signal during a calibration phase, and generates a reference computation value by a multiply-accumulate operation according to the reference input signal and the reference weight value. The control circuit generates an adjustment value according to the reference computation value and a standard computation value, and during the computation phase, adjusts the computation result according to the adjustment value to generate an adjusted computation result.

Abstract: A multi-gate transistor includes; a doped drain region; a doped source region; a gate group including a first gate and a second gate; a channel, the doped drain region and the doped source region being on respective two sides of the channel; and an interlayer, formed between the channel and the gate group, wherein a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group, respectively, the channel is induced as at least a P sub-channel and at least an N sub-channel and the multi-gate transistor equivalently behaves as a PNPN structure.

Abstract: An artificial intelligence accelerator receives a binary input data set and a selected layer of layers of overall weight pattern. The artificial intelligence accelerator includes processing tiles and a summation output circuit. Each processing tile receives one of input data subsets of the input data set and performs a convolution operation on weight blocks of each sub weight pattern of the overall weight pattern to obtain weight operation values and then obtains a weight output value expected from a direct convolution operation on the input data subset with the sub weight pattern through performing a multistage shifting and adding operation on the weight operation values. The summation output circuit sums up the plurality of weight output values through a multistage shifting and adding operation, so as to obtain a sum value expected from a direct convolution operation performed on the input data set with the overall weight pattern.

Abstract: A multi-gate transistor includes: a doped drain region; a doped source region; a gate group including a first gate and a second gate; a channel, the doped drain region and the doped source region being on respective two sides of the channel; and an interlayer, formed between the channel and the gate group, wherein a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group, respectively, the channel is induced as at least a P sub-channel and at least an N sub-channel and the multi-gate transistor equivalently behaves as a PNPN structure.

Abstract: An integrated circuit and a computing method thereof are provided. The integrated circuit includes a memory array, word lines, bit lines and a page buffer. The memory array includes memory cells, each configured to be programmed with a weight. The word lines respectively connect a row of the memory cells. The bit lines are respectively connected with a column of the memory cells that are connected in series. More than one of the bit lines in a block of the memory array or more than one of the word lines in multiple blocks of the memory array are configured to receive input voltages. The memory cells receiving the input voltages are configured to multiply the weights stored therein and the received input voltages. The page buffer is coupled to the memory array, and configured to sense products of the weights and the input voltages.

Abstract: A semiconductor device includes a stack formed on a substrate and memory strings penetrating the stack along a first direction. The stack includes conductive layers and insulating layers that alternately stacked. Each of the memory strings includes a channel layer, a memory structure, a first conductive pillar and a second conductive pillar. The channel layer, the first conductive pillar and the second conductive pillar extend along a first direction. The memory structure is disposed between the stack and the channel layer. The first conductive pillar and the second conductive pillar are electrically isolated from each other, and are respectively coupled to a first location and a second location of the channel layer. The first location is opposite to the second location. The first location is surrounded by the memory structure, and the second location is exposed from the memory structure.

Abstract: An in-memory computing device including a plurality of memory cell arrays and a plurality of sensing amplifiers are provided. The memory cell arrays respectively receive a plurality of input signals. The input signals are divided into a plurality of groups. The groups respectively have at least one partial input signal. The at least one partial input signal of each of the groups has a same value. Numbers of the at least one partial input signal in the groups sequentially form a geometric sequence with a common ration equal to 2. The memory cell arrays respectively provide a plurality of weightings, and perform multiply-add operations respectively according to the received input signals and the weightings to generate a plurality of computation results. The sensing amplifiers respectively generate a plurality of sensing results according to the computation results.

Abstract: The present disclosure relates to a non-volatile memory and operating method thereof. The non-volatile memory includes multiple memory strings, multiple bit switch units, a memory operation circuit and multiple source switch units. The bit switch units are electrically connected to the memory strings. The memory operation circuit is electrically connected to the bit switch units to transmit a write signal to the memory unit strings. The source switch units are electrically connected to the memory string so that the memory strings receive a bias signal via the source switch unit. In a program mode, when a first bit switch unit of the bit switch units is turned on and a first memory strings receives the write signal through the first bit switch unit, the source switch units electrically connected to the other memory strings will be turned on.

Abstract: An integrated circuit and a computing method thereof are provided. The integrated circuit includes a memory array, word lines, bit lines and a page buffer. The memory array includes memory cells, each configured to be programmed with a weight. The word lines respectively connect a row of the memory cells. The bit lines are respectively connected with a column of the memory cells that are connected in series. More than one of the bit lines in a block of the memory array or more than one of the word lines in multiple blocks of the memory array are configured to receive input voltages. The memory cells receiving the input voltages are configured to multiply the weights stored therein and the received input voltages. The page buffer is coupled to the memory array, and configured to sense products of the weights and the input voltages.

Abstract: A device based on 2T vertical ferroelectric memory cells includes a plurality of select gate lines in a first layer, and a plurality of word lines in a second layer, with a plurality of vertical channel structures disposed operably with the select gate lines and word lines. A vertical channel structure of a memory cell in the plurality is disposed orthogonally relative to a corresponding select gate line and a corresponding word line, and forms a channel for the vertical select transistor and the vertical ferroelectric memory transistor. Ferroelectric material is disposed at cross-points between the vertical channel structure and the corresponding word line. A gate dielectric material is disposed at cross-points between the vertical channel structure and the corresponding select gate line. A NOR architecture memory uses the 2T vertical ferroelectric memory cells.

Abstract: A 3D flash memory is provided to includes a gate stack structure comprising a plurality of gate layers electrically insulated from each other, a cylindrical channel pillar vertically extending through each gate layer of the gate stack structure, a first conductive pillar vertically extending through the gate stack structure, the first conductive pillar being located within the cylindrical channel pillar and being electrically connected to the cylindrical channel pillar, and a second conductive pillar extending through the gate stack structure, the second conductive pillar being located within the cylindrical channel pillar and being electrically connected to the cylindrical channel pillar, the first conductive pillar and the second conductive pillar being separated from each other. The 3D flash memory also includes a ferroelectric layer disposed between gate layers of the gate stack structure and the cylindrical channel pillar.

Abstract: A device based on 2T vertical ferroelectric memory cells includes a plurality of select gate lines in a first layer, and a plurality of word lines in a second layer, with a plurality of vertical channel structures disposed operably with the select gate lines and word lines. A vertical channel structure of a memory cell in the plurality is disposed orthogonally relative to a corresponding select gate line and a corresponding word line, and forms a channel for the vertical select transistor and the vertical ferroelectric memory transistor. Ferroelectric material is disposed at cross-points between the vertical channel structure and the corresponding word line. A gate dielectric material is disposed at cross-points between the vertical channel structure and the corresponding select gate line. A NOR architecture memory uses the 2T vertical ferroelectric memory cells.

Abstract: A three-dimensional (3D) flash memory module, a healing method of 3D flash memory, and an operating method of 3D flash memory are provided. The 3D flash memory module includes a 3D flash memory structure and a conductive layer. The 3D flash memory structure is disposed on a substrate. The conductive layer is disposed on the substrate and is adjacent to at least one side wall of the 3D flash memory structure. The conductive layer extends along the at least one side wall of the 3D flash memory structure, and each of two opposite end portions of the conductive layer has an electrical connection point in an extending direction of the conductive layer.

Abstract: A three-dimensional memory device includes a substrate, a plurality of conductive layers and insulating layers, a memory layer stack, an isolation portion, a second hole and a dielectric filler. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The multi-layer stacked structure includes multiple first holes, and each first hole passing through the conductive layers and the insulating layers. The memory layer stack has a first string portion, a second string portion and a bottom string portion connected between the first and second string portions. The isolation portion is embedded among the first, second and bottom string portions of each of the memory layer stacks in the first holes. The dielectric filler is located on the isolation portion and has side protrusions in contact with the conductive layers.

Abstract: A flash memory device and a controlling method are provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The in-place update module is used for performing a program procedure or a garbage collection procedure via a bit erase operation or a page erase operation on the memory array. The out-of-place update module is used for performing the program procedure or the garbage collection procedure via a block erase operation or a migration operation on the memory array. The latency-aware module is used for determining a relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module.

Abstract: A three-dimensional (3D) flash memory module, a healing method of 3D flash memory, and an operating method of 3D flash memory are provided. The 3D flash memory module includes a 3D flash memory structure and a conductive layer. The 3D flash memory structure is disposed on a substrate. The conductive layer is disposed on the substrate and is adjacent to at least one side wall of the 3D flash memory structure. The conductive layer extends along the at least one side wall of the 3D flash memory structure, and each of two opposite end portions of the conductive layer has an electrical connection point in an extending direction of the conductive layer.

Abstract: Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.

Abstract: Roughly described, the invention involves a device including a memory chip having a memory array, bit lines in communication with data carrying nodes of the memory array, and word lines in communication with certain gate control nodes of the memory array. The memory chip has bonding pads formed on an interconnect surface at respective memory chip interconnect locations. Each of the bit lines and each of the word lines of the memory array includes a respective landing pad in a conductive layer of the chip, and these landing pads connected via redistribution conductors to respective ones of the set of memory chip bonding pads. The redistribution conductors for the bit lines have a positive average lateral signal travel distance which is less than that of the redistribution conductors for the word lines.

Abstract: A 3D memory device includes a multi-layers stacking structure having an O-shaped opening; a memory structure layer having a first string portion and a second string portion disposed on two opposite sides of a sidewall of the O-shaped opening and a connection portion disposed on a bottom of the O-shaped opening and connecting the first and the second string portion; a dielectric pillar disposed in the O-shaped opening and over the connection portion; an isolation body extending along a direction and embedded among the first string portion, the second string portion and the connection portion to isolate the first string portion from the second string portion; a first contact disposed in a first recess defined by the first string portion, the dielectric pillar and the isolation body; and a second contact disposed in a second recess defined by the second string portion, the dielectric pillar and the isolation body.

Abstract: An AND type flash memory includes a memory cell array, a plurality of page buffers and a plurality of voltage shifting circuits. The memory cell array is coupled to a plurality of bits lines and source lines. The page buffers are respectively coupled to the bit lines through a plurality of switches, and respectively provides a plurality of control signals. The control signals are transited between a first voltage and a reference voltage. The voltage shifting circuits respectively receive the control signals, generates a plurality of driving signals by shifting voltage values of the control signals, and provides the driving signals to the bit lines. Wherein, the driving signals are transited between a second voltage and the reference voltage, the second voltage is larger than the first voltage.