Abstract: A three-dimensional memory device includes a substrate, a plurality of conductive layers and insulating layers, a memory layer stack, an isolation portion, a second hole and a dielectric filler. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The multi-layer stacked structure includes multiple first holes, and each first hole passing through the conductive layers and the insulating layers. The memory layer stack has a first string portion, a second string portion and a bottom string portion connected between the first and second string portions. The isolation portion is embedded among the first, second and bottom string portions of each of the memory layer stacks in the first holes. The dielectric filler is located on the isolation portion and has side protrusions in contact with the conductive layers.

Abstract: A device comprises a 3D array of cells arranged for execution of a sum-of-products operation, the cells in the 3D array disposed in cross-points of a plurality of vertical lines and a plurality of horizontal lines, the cells having programmable conductances. A gate driver is coupled to gate lines which applies control gate voltages which in combination with the programmable conductances of the cells correspond to weights Wxyz of terms in the sum-of-products operation. An input driver applies voltages to cells in the array corresponding to input variables Xy. A sensing circuit senses a sum of currents from cells in the 3D array corresponding to the sum-of-products.

Abstract: A 3D memory array device includes blocks, bit lines, word lines, source lines (SL), complementary metal oxide semiconductors (COMS), and SL sensing amplifiers (SA). Each block includes NAND strings, and each memory cell in the NAND strings stores one or more weights. The bit lines are respectively coupled as signal inputs to string select lines in all blocks. The word lines are respectively coupled to the memory cells, and the word lines in the same layer are as a convolution layer to perform a convolution operation on the inputted signal. Different SL are coupled to all ground select lines in different blocks to independently collect a total current of the NAND strings in each block. The CMOS are disposed under the blocks and coupled to each source line for transferring the total current to each SL SA, and a multiply-accumulate result of each block is outputted via each SL SA.

Abstract: A 3D memory device includes a multi-layers stacking structure having a plurality of conductive layers and insulating layers stacked in a staggered manner, at least one trench passing through the conductive layers and a plurality of recess regions extending into the conductive layers from the trench; a dielectric blocking strip lining sidewalls of the trench and the recess regions; a plurality of floating gates disposed in the recess regions and isolated from the conductive layers by the dielectric blocking strip; a dielectric strip overlies sidewalls of the floating gates exposed from the recess regions; a semiconductor strip disposed in the trench, insulated from the floating gates by the dielectric strip, and includes a first doping region, a second doping region and a channel region disposed between and connects to the first doping region and the second doping region, and overlapping with the floating gates.

Abstract: A flash memory device and a controlling method are provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The in-place update module is used for performing a program procedure or a garbage collection procedure via a bit erase operation or a page erase operation on the memory array. The out-of-place update module is used for performing the program procedure or the garbage collection procedure via a block erase operation or a migration operation on the memory array. The latency-aware module is used for determining a relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module.

Abstract: A 3D memory device includes a multi-layers stacking structure having an O-shaped opening; a memory structure layer having a first string portion and a second string portion disposed on two opposite sides of a sidewall of the O-shaped opening and a connection portion disposed on a bottom of the O-shaped opening and connecting the first and the second string portion; a dielectric pillar disposed in the O-shaped opening and over the connection portion; an isolation body extending along a direction and embedded among the first string portion, the second string portion and the connection portion to isolate the first string portion from the second string portion; a first contact disposed in a first recess defined by the first string portion, the dielectric pillar and the isolation body; and a second contact disposed in a second recess defined by the second string portion, the dielectric pillar and the isolation body.

Abstract: A circuit for in-memory multiply-and-accumulate functions includes a plurality of NAND blocks. A NAND block includes an array of NAND strings, including B columns and S rows, and L levels of memory cells. W word lines are coupled to (B*S) memory cells in respective levels in the L levels. A source line is coupled to the (B*S) NAND strings in the block. String select line drivers supply voltages to connect NAND strings on multiple string select lines to corresponding bit lines simultaneously. Word line drivers are coupled to apply word line voltages to a word line or word lines in a selected level. A plurality of bit line drivers apply input data to the B bit lines simultaneously. A current sensing circuit is coupled to the source line.

Abstract: A neural network system for execution of a sum-of-products operation includes a memory device and a controller. The memory device includes a 3D array having a plurality of memory cells with programmable conductances disposed in cross-points of a plurality of cell body lines and gate lines, a gate driver coupled to the gate lines and applying control gate voltages in combination with the programmable conductances for corresponding to weights of terms in the sum-of-products operation, a input driver used to apply voltages to the memory cells corresponding to input variables, a plurality of input lines connecting the cell body lines to the input driver, a sensing circuit used to sense currents passing through the memory cells corresponding the terms in the sum-of-products operation, a buffer circuit used to store the terms. The controller is used to control the memory device summing up the terms in the sum-of-products operation.

Abstract: A memory device comprises a stack of conductive strips separated by insulating strips, the conductive strips in the stack extending in a first direction. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through the conductive strips in the stack, each of the hemi-cylindrical vertical channel structures having a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures on the sidewalls of the conductive strips. The hemi-cylindrical vertical channel structures comprise semiconductor films having outside surfaces in contact with the data storage structures on the sidewalls of the conductive strips.

Abstract: A memory device comprises a stack of conductive strips separated by insulating strips, the conductive strips in the stack extending in a first direction. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through the conductive strips in the stack, each of the hemi-cylindrical vertical channel structures having a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures on the sidewalls of the conductive strips. The hemi-cylindrical vertical channel structures comprise semiconductor films having outside surfaces in contact with the data storage structures on the sidewalls of the conductive strips.

Abstract: A memory device comprises a reference conductor, and a stack of conductive strips separated by insulating strips, where the conductive strips in the stack extend in a first direction, and the stack is disposed on the reference conductor. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through respective vias in the conductive strips in the stack, and comprising semiconductor films in electrical contact with the reference conductor having outside surfaces. Each of the hemi-cylindrical vertical channel structures has a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures between the outside surfaces of the semiconductor films and sidewalls of the vias in the conductive strips.

Abstract: A neural network system for execution of a sum-of-products operation includes a memory device and a controller. The memory device includes a 3D array having a plurality of memory cells with programmable conductances disposed in cross-points of a plurality of cell body lines and gate lines, a gate driver coupled to the gate lines and applying control gate voltages in combination with the programmable conductances for corresponding to weights of terms in the sum-of-products operation, a input driver used to apply voltages to the memory cells corresponding to input variables, a plurality of input lines connecting the cell body lines to the input driver, a sensing circuit used to sense currents passing through the memory cells corresponding the terms in the sum-of-products operation, a buffer circuit used to store the terms. The controller is used to control the memory device summing up the terms in the sum-of-products operation.

Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.

Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.

Abstract: A memory device includes a plurality of stacks of conductive strips alternating with insulating strips, the insulating strips having first and second sides, and the conductive strips having first sidewalls recessed relative to the first sides of the insulating strips which define first recessed regions in sides of the stacks. Vertical channel pillars are disposed between the stacks, the vertical channel pillars having first and second channel films disposed on adjacent stacks and a dielectric material between and contacting the first and second channel films. Data storage structures at cross points of the vertical channel pillars and the conductive strips include tunneling layers in contact with the vertical channel pillars, discrete charge trapping elements in the first recessed regions in contact with the tunneling layers and blocking layers between the discrete charge trapping elements and the first sidewalls of the conductive strips.

Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.

Abstract: A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i?1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i?1).

Abstract: A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.

Abstract: A device comprises a 3D array of cells arranged for execution of a sum-of-products operation, the cells in the 3D array disposed in cross-points of a plurality of vertical lines and a plurality of horizontal lines, the cells having programmable conductances. A gate driver is coupled to gate lines which applies control gate voltages which in combination with the programmable conductances of the cells correspond to weights Wxyz of terms in the sum-of-products operation. An input driver applies voltages to cells in the array corresponding to input variables Xy. A sensing circuit senses a sum of currents from cells in the 3D array corresponding to the sum-of-products.

Abstract: A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.