Patents by Inventor Hao CHU

Hao CHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230040297
    Abstract: A projection device includes a housing, a projection module, a fan, and at least one stopper wall structure. The housing has an air inlet, a first air outlet, and at least one second air outlet. The fan has a wind outlet facing the first air outlet. One part of the projection module is located between the wind outlet and the first air outlet, and one part of a heat dissipating airflow provided by the fan flows from the wind outlet to the first air outlet. The stopper wall structure is connected to the fan, and the stopper wall structure and one part of the housing define at least one air guiding channel. The other part of the projection module is located in the air guiding channel, and the other part of the heat dissipating airflow is guided by the air guiding channel to flow toward the second air outlet.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 9, 2023
    Applicant: Coretronic Corporation
    Inventors: Meng-Syuan Dai, Wen-Hao Chu
  • Publication number: 20230032773
    Abstract: A sensing system is disclosed. The sensing system includes a sensor cartridge and a readout device. The sensor cartridge includes a sensing device and a micro-channel-structure. The sensing device includes a chip member and an electrode member arranged projectively offset from each other.
    Type: Application
    Filed: December 23, 2020
    Publication date: February 2, 2023
    Inventors: CHIH-CHEN LIN, CHIA-NAN CHIEN, JUNG-HSIN WU, TSUNG-CHIH HUANG, CHIH-HAO CHU, TIEH-KANG WU, SHENG-YU SHIAO
  • Patent number: 11546320
    Abstract: A method for controlling the IoT devices and an IoT system using the same are provided. The IoT devices includes a trigger device and a functional device. A managing software is executable on a client device. First, a credential is sent to the client from the functional device. Second, a script is received at the trigger device. The script includes the credential, at least one supported command, and at least one supported event. The script is generated at the managing software. The supported command is recognizable to the functional device. When the supported event is triggered at the trigger device, the supported command from the trigger device is received at the functional device. Then, a function of the functional device is performed based on the command, which increases the convenience of operating the system. The trigger device need not recognize the command, which increases the flexibility of the system.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: January 3, 2023
    Assignees: THROUGHTEK CO., LTD., THROUGHTEK TECHNOLOGY (SHENZHEN) CO., LTD.
    Inventors: Chung-Han Yang, Ying-Hao Chu, Kai-Kuo Liu
  • Publication number: 20220365410
    Abstract: Provided is a projection device, including a casing, a light source module, an optical engine module, a projection lens, and a fan. The casing includes a right cover plate and a baffle opposite to each other, and a lower cover plate adjacent to the right cover plate. The baffle divides the casing into first and second areas. The right and lower cover plates respectively have first and second air outlets adjacent to each other and located in the second area. The light source module, the optical engine module, located on a light transmission path of the light source module, the projection lens, connected to the optical engine module, and the fan, adjacent to the baffle, are disposed in the first area of the casing. The projection device is placed in a first or second state, and hot airflow therein flows out from the first or second air outlet.
    Type: Application
    Filed: July 20, 2021
    Publication date: November 17, 2022
    Applicant: Coretronic Corporation
    Inventors: Jui-Cheng Tseng, Wen-Hao Chu
  • Publication number: 20220367634
    Abstract: Provided is a semiconductor device including a substrate having a lower portion and an upper portion on the lower portion; an isolation region disposed on the lower portion of the substrate and surrounding the upper portion of the substrate in a closed path; a gate structure disposed on and across the upper portion of the substrate; source and/or drain (S/D) regions disposed in the upper portion of the substrate at opposite sides of the gate structure; and a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region and the S/D regions have different conductivity types, and the channel region and the substrate have the same conductivity type.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu
  • Publication number: 20220359275
    Abstract: A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu, Ching-Yu Yang
  • Publication number: 20220310395
    Abstract: A method of manufacturing a semiconductor structure, comprising providing a substrate; forming a fin structure over the substrate; depositing an insulation material over the fin structure; performing a plurality of ion implantation cycles in-situ with implantation energy increased or decreased stepwise; and removing at least a portion of the insulation material to expose a portion of the fin structure.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Inventors: CHIA-CHUNG CHEN, CHUNG-HAO CHU, CHI-FENG HUANG, VICTOR CHIANG LIANG
  • Patent number: 11456355
    Abstract: Provided is a semiconductor device including a substrate having a first conductivity type; an isolation structure disposed in the substrate to form an active region in the substrate; a well region having the first conductivity type, extending from an inner sidewall of the isolation structure into the active region, wherein a portion of the substrate is surrounded by the well region to form a native region in the active region; a gate structure disposed over the active region; and doped regions having a second conductivity type, disposed respectively in the active region at two sides of the gate structure, wherein a portion of the native region is sandwiched between the doped regions to form a channel region below the gate structure, and a doping concentration of the channel region is substantially equal to a doping concentration of the substrate.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu
  • Patent number: 11443980
    Abstract: A method of fabricating a semiconductor device includes at least the following steps is provided. A first metal layer is formed on a substrate. A first dielectric layer is formed on the substrate. The first dielectric layer is patterned, thereby forming a first opening exposing the first metal layer. A second metal layer is formed on the first dielectric layer and filling into the first opening. The second metal layer is patterned, thereby forming a metal pad. A second dielectric layer is formed on the first dielectric layer and the metal pad. The second dielectric layer is patterned, thereby forming a second opening exposing the metal pad. A first annealing process is performed in an atmosphere of a gas including 50 vol % to 100 vol % of hydrogen.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu, Ching-Yu Yang
  • Patent number: 11380548
    Abstract: A method of manufacturing a semiconductor structure, comprising providing a substrate; forming a fin structure over the substrate; depositing an insulation material over the fin structure; performing a plurality of ion implantations in-situ with implantation energy increased or decreased stepwise; and removing at least a portion of the insulation material to expose a portion of the fin structure.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chung Chen, Chung-Hao Chu, Chi-Feng Huang, Victor Chiang Liang
  • Patent number: 11330163
    Abstract: In an embodiment, a camera sensor module is communicatively coupled to a vision processing system. The camera sensor module captures a plurality of exposures, produces an HDR-combined stream, and sends both the HDR-combined stream and the plurality of exposures to the vision processing system. A first ISP of the vision processing system performs color processing to produce a color-processed HDR-combined stream for neural network processing, presentation to a human, and/or computer vision processing. At least one other ISP of the vision processing system performs color processing to collect exposure-specific statistics on at least one of the plurality of exposures for determining camera calibration data for the camera sensor module.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 10, 2022
    Assignee: QUALCOMM Incorporated
    Inventor: Jeffrey Hao Chu
  • Publication number: 20220100065
    Abstract: An optomechanical module, including an optomechanical housing, a light source, and a display element, is provided. The optomechanical housing includes at least one heat-dissipation hole. The light source is configured to emit an illumination beam and is disposed in the optomechanical housing. The display element is disposed in the optomechanical housing, is located on a transmission path of the illumination beam, and is configured to convert the illumination beam into an image beam. When the optomechanical module operates, the light source generates heat, and the at least one heat-dissipation hole is configured to allow airflow to pass through, so as to dissipate the heat generated by the light source. A projector is also provided.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 31, 2022
    Applicant: Coretronic Corporation
    Inventors: Kuang-Hsiang Chang, Wen-Hao Chu, Li-Wei Tseng
  • Patent number: 11264486
    Abstract: The present disclosure provides a semiconductor device, including a substrate, a fin over the substrate, wherein the fin extends along a primary direction, a gate over the fin, the gate extends along the secondary direction orthogonal to the primary direction, a first conductive contact over the gate, and a conductive routing layer over the first conductive contact, wherein at least a portion of the fin is free from the coverage of a vertical projection of the conductive routing layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Hao Chu, Chia-Chung Chen, Shu Fang Fu, Chi-Feng Huang, Victor Chiang Liang
  • Publication number: 20210379032
    Abstract: The present disclosure generally relates to compounds class I HDAC inhibitors, their production and applications. The compounds possess epigenetic immunomodulatory activities in the tumor microenvironment (TME) and thus inhibit growth of tumor cells.
    Type: Application
    Filed: April 28, 2021
    Publication date: December 9, 2021
    Inventors: Jia-Shiong CHEN, Mu-Hsuan YANG, Yi-Hong WU, Sz-Hao CHU, Cheng-Han CHOU, Ye-Su CHAO, Chia-Nan CHEN
  • Publication number: 20210334086
    Abstract: A method is provided for adding a sensor monitoring feature of a newly-added sensor to a system monitoring feature provided by a baseboard management controller (BMC). The BMC stores a BMC firmware that contains a main program, a sensor library and a sensor data record. The BMC updates the sensor library to a target sensor library that includes identification information of the additional sensor, and functions used to execute the sensor monitoring feature of the additional sensor. By executing the main program, the BMC loads the target sensor library, and adds the identification information of the additional sensor to the sensor data record.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 28, 2021
    Inventor: Hsin-Hao CHU
  • Patent number: 11148675
    Abstract: Examples disclosed herein provide mechanisms for controlling a sensor in a multiple System on Chip (SoC) environment that allows one of the multiple System on Chips to be selected as a host System on Chip. The host System on Chip may lock the sensor to apply setting updates only from the host System on Chip that has locked the sensor. This lock may be broadcast to all sensors over an embedded data channel sent to all System on Chips receiving the sensor data. In addition, a safety monitor may be included to detect if the host System on Chip is functioning properly so that another System on Chip may be selected as a new host System on Chip.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: October 19, 2021
    Assignee: QUALCOMM Incorporated
    Inventor: Jeffrey Hao Chu
  • Patent number: 11145729
    Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal layer, and a semiconductor layer. The metal layer is disposed on the gate dielectric layer. The semiconductor layer is disposed on the gate dielectric layer. The metal layer surrounds the semiconductor layer.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Meng-Chang Ho, Chung-Hao Chu, Tz-Hau Guo
  • Patent number: 11126048
    Abstract: An array substrate includes gate lines, data lines, and pixel units defined by adjacent gate lines and adjacent data lines, the gate lines, the data lines, and the pixel units being formed on a substrate, wherein the gate line gradually becomes wider from a driving start end to a driving terminal end. on the array substrate.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 21, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hao Chu, Yue Shi, Chuanbao Chen
  • Patent number: 11088136
    Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a substrate, a growth promoting region, a first gate stack, and a second gate stack. The substrate includes a first region and a second region. The growth promoting region is located in a surface of the substrate in the first region. The growth promoting region includes a first implantation species, and a surface of the substrate in the second region is free of the first implantation species. The first gate stack includes a first gate dielectric layer on the substrate in the first region. The second gate stack includes a second gate dielectric layer on the substrate in the second region.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • Publication number: 20210226043
    Abstract: The present disclosure provides a semiconductor device, including a substrate, a fin over the substrate, wherein the fin extends along a primary direction, a gate over the fin, the gate extends along the secondary direction orthogonal to the primary direction, a first conductive contact over the gate, and a conductive routing layer over the first conductive contact, wherein at least a portion of the fin is free from the coverage of a vertical projection of the conductive routing layer.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Inventors: CHUNG-HAO CHU, CHIA-CHUNG CHEN, SHU FANG FU, CHI-FENG HUANG, VICTOR CHIANG LIANG