Patents by Inventor Hao CHU

Hao CHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210202252
    Abstract: A method of manufacturing a semiconductor structure, comprising providing a substrate; forming a fin structure over the substrate; depositing an insulation material over the fin structure; performing a plurality of ion implantations in-situ with implantation energy increased or decreased stepwise; and removing at least a portion of the insulation material to expose a portion of the fin structure.
    Type: Application
    Filed: May 26, 2020
    Publication date: July 1, 2021
    Inventors: CHIA-CHUNG CHEN, CHUNG-HAO CHU, CHI-FENG HUANG, VICTOR CHIANG LIANG
  • Publication number: 20210181042
    Abstract: A bending sensing device comprises a substrate, a piezoresistive thin film and at least a pair of electrodes. The substrate is flexible and having a two-dimensional structure, and a material of the substrate is mica. The piezoresistive thin film is disposed on the substrate whose material is inorganic compound comprising zinc oxide (ZnO), doped ZnO, germanium (Ge), doped Ge, or any combinations thereof. The at least a pair of electrodes are disposed separately on two terminals of at least a measurement section of the piezoresistive thin film to electrically connect the measurement section.
    Type: Application
    Filed: July 3, 2020
    Publication date: June 17, 2021
    Inventors: Ying-Hao Chu, Min Yen
  • Patent number: 10991688
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a gate stack, a first doped region, a second doped region, and a buried doped region. The first doped region has a first conductivity type and is located in the substrate at a first side of the gate stack. The second doped region has the first conductivity type and is located in the substrate at a second side of the gate stack. The buried doped region has the first conductivity type and is buried in the substrate, extended from the first doped region to the second doped region, and separated from the gate stack by a distance.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • Publication number: 20210098286
    Abstract: A method of fabricating a semiconductor device includes at least the following steps is provided. A first metal layer is formed on a substrate. A first dielectric layer is formed on the substrate. The first dielectric layer is patterned, thereby forming a first opening exposing the first metal layer. A second metal layer is formed on the first dielectric layer and filling into the first opening. The second metal layer is patterned, thereby forming a metal pad. A second dielectric layer is formed on the first dielectric layer and the metal pad. The second dielectric layer is patterned, thereby forming a second opening exposing the metal pad. A first annealing process is performed in an atmosphere of a gas including 50 vol % to 100 vol % of hydrogen.
    Type: Application
    Filed: May 26, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu, Ching-Yu Yang
  • Publication number: 20210069163
    Abstract: The present invention relates to a combination of a histone deacetylase (HDAC) inhibitor, chidamide in an acidic salt form, and a nonsteroidal anti-inflammatory drugs (NSAIDs), celecoxib in a basic salt form. The present invention also relates to methods which significantly regulate tumor microenvironment and therefore dramatically improve anti-cancer activity.
    Type: Application
    Filed: September 10, 2019
    Publication date: March 11, 2021
    Inventors: Jia-Shiong CHEN, Mu-Hsuan YANG, Cheng-Han CHOU, Yi-Hong WU, Sz-Hao CHU, Ye-Su CHAO, Chia-Nan CHEN
  • Patent number: 10944115
    Abstract: A cathode layer and a membrane electrode assembly of a solid oxide fuel cell are provided. The cathode layer consists of a plurality of perovskite crystal films, and the average change rate of linear thermal expansion coefficients of these perovskite crystal films is about 5% to 40% along the thickness direction. The membrane electrode assembly includes the above-mentioned cathode layer, and the linear thermal expansion coefficients of these perovskite crystal films are reduced towards the solid electrolyte layer of the membrane electrode assembly.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: March 9, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Tzu-Chi Chou, Kuo-Chuang Chiu, Tzu-Yu Liu, Yung-Hsiang Juan, Ying-Hao Chu
  • Patent number: 10930496
    Abstract: A method for fabricating heteroepitaxial semiconductor material on a mica sheet is disclosed. Firstly, a mica substrate is provided. Then, at least one semiconductor film is deposited on the mica substrate to form a flexible substrate whose flexibility is applied to various applications, such as wearable devices, portable photoelectric equipment, or improving the speed and bandwidth of commercial and military systems, such that the flexible substrate has the competitiveness in the market.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: February 23, 2021
    Assignee: National Chiao Tung University
    Inventors: Yi-Chia Chou, Wan-Jung Lo, Ying-Hao Chu
  • Patent number: 10911730
    Abstract: A projector including a casing, at least one fan, a light source module, a light valve module and a projection lens is provided. The casing has a first air inlet, a second air inlet and an air outlet. The fan is disposed in the casing and adjacent to the air outlet. The light source module is disposed in the casing and adapted to provide an illumination light beam. The light valve module is disposed in the casing and adjacent to the second air inlet, and is adapted to convert the illumination light beam into an image light beam. The light source module and the light valve module at least partially overlap with each other along a first direction perpendicular to an opening of the first air inlet. The projection lens is disposed on the casing and adapted to project the image light beam out of the projector.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: February 2, 2021
    Assignee: Coretronic Corporation
    Inventors: Chao-Nan Chien, Wen-Hao Chu, Tung-Chou Hu
  • Patent number: 10859898
    Abstract: A projection apparatus and a heat dissipation control method thereof are provided. The projection apparatus includes a light valve module, a light source, a brightness sensor, a cooling element, a first temperature sensor, a second temperature sensor and a controller. The controller determines a specified temperature of the cooling element according to the brightness of an illumination beam provided by the light source, and calculates a dew point temperature according to the ambient temperature. The controller adjusts the operating power of the cooling element according to the dew point temperature, the specified temperature and the cold end temperature of the cold end surface of the cooling element. The operating power of the cooling element is flexibly adjusted based on the brightness provided by the light source to avoid a dew formation phenomenon on the cooling element and the light valve module.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: December 8, 2020
    Assignee: Coretronic Corporation
    Inventors: Kai-Lun Hou, Wen-Hao Chu, Te-Tang Chen
  • Publication number: 20200341358
    Abstract: A projection apparatus and a heat dissipation control method thereof are provided. The projection apparatus includes a light valve module, a light source, a brightness sensor, a cooling element, a first temperature sensor, a second temperature sensor and a controller. The controller determines a specified temperature of the cooling element according to the brightness of an illumination beam provided by the light source, and calculates a dew point temperature according to the ambient temperature. The controller adjusts the operating power of the cooling element according to the dew point temperature, the specified temperature and the cold end temperature of the cold end surface of the cooling element. The operating power of the cooling element is flexibly adjusted based on the brightness provided by the light source to avoid a dew formation phenomenon on the cooling element and the light valve module.
    Type: Application
    Filed: April 23, 2020
    Publication date: October 29, 2020
    Applicant: Coretronic Corporation
    Inventors: Kai-Lun Hou, Wen-Hao Chu, Te-Tang Chen
  • Publication number: 20200295137
    Abstract: Provided is a semiconductor device including a substrate having a first conductivity type; an isolation structure disposed in the substrate to form an active region in the substrate; a well region having the first conductivity type, extending from an inner sidewall of the isolation structure into the active region, wherein a portion of the substrate is surrounded by the well region to form a native region in the active region; a gate structure disposed over the active region; and doped regions having a second conductivity type, disposed respectively in the active region at two sides of the gate structure, wherein a portion of the native region is sandwiched between the doped regions to form a channel region below the gate structure, and a doping concentration of the channel region is substantially equal to a doping concentration of the substrate.
    Type: Application
    Filed: May 31, 2020
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu
  • Publication number: 20200272003
    Abstract: An array substrate includes gate lines, data lines, and pixel units defined by adjacent gate lines and adjacent data lines, the gate lines, the data lines, and the pixel units being formed on a substrate, wherein the gate line gradually becomes wider from a driving start end to a driving terminal end.
    Type: Application
    Filed: September 22, 2017
    Publication date: August 27, 2020
    Inventors: Hao CHU, Yue SHI, Chuanbao CHEN
  • Publication number: 20200243658
    Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal layer, and a semiconductor layer. The metal layer is disposed on the gate dielectric layer. The semiconductor layer is disposed on the gate dielectric layer. The metal layer surrounds the semiconductor layer.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Meng-Chang Ho, Chung-Hao Chu, Tz-Hau Guo
  • Publication number: 20200234944
    Abstract: A method for fabricating heteroepitaxial semiconductor material on a mica sheet is disclosed. Firstly, a mica substrate is provided. Then, at least one semiconductor film is deposited on the mica substrate to form a flexible substrate whose flexibility is applied to various applications, such as wearable devices, portable photoelectric equipment, or improving the speed and bandwidth of commercial and military systems, such that the flexible substrate has the competitiveness in the market.
    Type: Application
    Filed: April 17, 2019
    Publication date: July 23, 2020
    Inventors: YI-CHIA CHOU, WAN-JUNG LO, YING-HAO CHU
  • Publication number: 20200220860
    Abstract: A method for controlling the IoT devices and an IoT system using the same are provided. The IoT devices includes a trigger device and a functional device. A managing software is executable on a client device. First, a credential is sent to the client from the functional device. Second, a script is received at the trigger device. The script includes the credential, at least one supported command, and at least one supported event. The script is generated at the managing software. The supported command is recognizable to the functional device. When the supported event is triggered at the trigger device, the supported command from the trigger device is received at the functional device. Then, a function of the functional device is performed based on the command, which increases the convenience of operating the system. The trigger device need not recognize the command, which increases the flexibility of the system.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 9, 2020
    Inventors: Chung-Han Yang, Ying-Hao Chu, Kai-Kuo Liu
  • Patent number: 10699642
    Abstract: Provided are a pixel circuit and driving method thereof, array substrate and display device. The pixel circuit includes a light-emitting element, a driving sub-circuit, a scanning sub-circuit, and a carrier releasing sub-circuit. The driving sub-circuit is connected to a first electrode of light-emitting element, and the driving sub-circuit is configured to store a driving voltage and control the magnitude of a current passing through light-emitting element according to the driving voltage; the scanning sub-circuit is connected to driving sub-circuit.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 30, 2020
    Assignees: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventors: Juncai Ma, Hao Chu
  • Publication number: 20200194430
    Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a substrate, a growth promoting region, a first gate stack, and a second gate stack. The substrate includes a first region and a second region. The growth promoting region is located in a surface of the substrate in the first region. The growth promoting region includes a first implantation species, and a surface of the substrate in the second region is free of the first implantation species. The first gate stack includes a first gate dielectric layer on the substrate in the first region. The second gate stack includes a second gate dielectric layer on the substrate in the second region.
    Type: Application
    Filed: February 25, 2020
    Publication date: June 18, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • Patent number: 10672873
    Abstract: Provided is a semiconductor device including a substrate having a first conductivity type, an isolation structure, a well region having the first conductivity type, a gate structure, and doped regions having a second conductivity type. The isolation structure is disposed in the substrate to form an active region of the substrate. The well region is disposed in the active region and surrounds sidewalls of the isolation structure to form a native region in the active region. The gate structure is disposed over the substrate in the native region. The doped regions are disposed respectively in the well region and the native region of the substrate at two sides of the gate structure. A method of fabricating the semiconductor device is also provided.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu
  • Patent number: 10658478
    Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal layer, and a semiconductor layer. The metal layer is disposed on the gate dielectric layer. The semiconductor layer is disposed on the gate dielectric layer. The metal layer surrounds the semiconductor layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Meng-Chang Ho, Chung-Hao Chu, Tz-Hau Guo
  • Patent number: 10622351
    Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary