Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.

Abstract: An aspect of the disclosure includes a communication system and a communication method using reconfigurable intelligent surface and a reconfigurable intelligent surface device. The communication system includes at least one base station, a reconfigurable intelligent surface device, and a control at one least device. The at least one base station respectively transmits at least one beam. The reconfigurable intelligent surface device is coupled to the at least one base station, and measures the at least one beam of the at least one base station to obtain signal measurement results associated with each of the at least one base station. The control device is coupled to the at least one base station. The control device groups the at least one base station and the reconfigurable intelligent surface device into at least one group according to the signal measurement results associated with each of the at least one base station.

Abstract: Glasses with gesture recognition function include a glasses frame and a gesture recognition system. The gesture recognition system is disposed on the glasses frame and configured to detect hand gestures in front of the glasses thereby generating a control command. The gesture recognition system transmits the control command to an electronic device to correspondingly control the electronic device.

Abstract: An implant includes a substrate having an outer surface, a first layer disposed on the outer surface of the substrate, and a second layer disposed on the outer surface of the substrate. The first layer includes a polymeric material.

Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Abstract: Provided are a reticle defect inspection method and system. The reticle defect inspection method includes: a reticle is provided; a reticle defect inspection system is provided, and when the reticle is placed on a station or leaves the station, defect inspection is continuously performed on the reticle to obtain defect information of each defect; a dynamic threshold of each defect is obtained from the defect information of each defect; and whether the dynamic threshold of each defect belongs to a threshold unacceptable by the inspection system is judged, and if so, warning processing is performed.

Abstract: The present disclosure provides a privacy computing method based on homomorphic encryption, which includes steps as follows. The ciphertext data is received, where the ciphertext data has a floating-point homomorphic encryption data structure, and the floating-point homomorphic encryption data structure of the ciphertext data includes the ciphertext mantissa, exponent parameter and gain parameter. The gain parameter sets the precision of the floating point corresponding to the ciphertext mantissa. The exponent parameter is adapted to multiplication or division. The artificial intelligence model performs operations on the ciphertext data to return the ciphertext result.

Abstract: A power supply circuit is provided. The power factor correction (PFC) circuit is used to perform a power factor correction according to a first voltage to generate an intermediate voltage. The first storage capacitor is used to store a first electrical energy related to the intermediate voltage. The boost conversion circuit is connected to the PFC circuit and used to generate an output voltage according to the intermediate voltage. The boost conversion circuit includes a first post-stage inductor, a first post-stage diode and a first post-stage transistor. The second storage capacitor is used to store a second electrical energy related to the output voltage. The capacitance value of the second storage capacitor is less than the capacitance value of the first storage capacitor; the first electrical energy is completely or partially transferred as the second electrical energy.

Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.

Abstract: Methods, apparatuses, and computer-readable medium are provided for rate matching. An example method may include receiving a rate matching pattern configuration indicating at least a first control resource set (CORESET) in a first bandwidth part (BWP) and a second CORESET in a second BWP. The example method may also include receiving a physical downlink shared channel (PDSCH) in the first BWP. The example method may include processing the PDSCH transmission based on the rate matching pattern configuration, where the processing may include rate matching around resources of the first CORESET and first associated search space (SS) sets and the second CORESET and second associated SS sets.

Abstract: A computer-executable method for generating a side-by-side three-dimensional (3D) image includes the steps of creating a 3D mesh and estimating depth information of the raw image. The method further includes the steps of updating the left mesh area and the right mesh area of the 3D mesh based on the estimated depth information of the raw image and projecting each of the mesh vertices of the left mesh area onto a coordinate system of the side-by-side 3D image based on a left eye position, and projecting each of the mesh vertices of the right mesh area onto the coordinate system of the side-by-side 3D image based on a right eye position. The method further obtains the side-by-side 3D image by coloring the left mesh area and the right mesh area projected onto the coordinate system of the side-by-side 3D image based on the raw image.

Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.

Abstract: A manufacturing method of a silicon nitride thin film, a thin film transistor, and a display panel are disclosed, the method including: providing a silane precursor into an atomic layer deposition apparatus for a preset time period, and remaining the silane precursor for a preset time period; providing an inert gas thereinto for a preset time period for the first time, and purging the silane precursor; providing a nitrogen supplying precursor for a preset time period, and remaining the nitrogen supplying precursor for a preset time period; providing the inert gas for a preset time period for the second time, and purging the nitrogen supplying precursor; repeating for a preset number of times the steps of providing the silane precursor, providing the inert gas for the first time, providing the nitrogen supplying precursor and providing the inert gas for the second time to form the silicon nitride thin film.

Abstract: Apparatus, systems, and methods a crypto chat social software system can use the user's biological information to ensure the security of the account through a secure encryption method, which is not easy to be cracked, so that the user can fully control the security of his account. Encryption on each data generated by the user's application of social chat software is performed to ensure that only the users themselves can view the application's data and digital assets. The server storage can be decentralized in that al data stored and backed up are encrypted information. Accordingly, users' private data and digital assets cannot be stolen and abused. At the same time, the user's data will not be affected, the user still owns, and only the user owns their private data and digital assets.

Abstract: A backlight module including a light guide plate, a light source, an upper prism sheet, and a lower prism sheet is provided. The light guide plate has a light incident surface and a light emitting surface. The upper prism sheet is disposed at a side of the light emitting surface of the light guide plate. The upper prism sheet includes an upper substrate and first prism microstructures. Cross-sections of the first prism microstructures are isosceles triangles, and apex angles thereof fall within a range of 80 to 90 degrees. The lower prism sheet is disposed between the light guide plate and the upper prism sheet. The lower prism sheet includes a lower substrate and second prism microstructures. Cross-sections of the second prism microstructures are isosceles triangles, and apex angles thereof fall within a range of 100 to 130 degrees.

Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: This disclosure provides systems, methods and apparatuses for enabling downlink throttling, such as for thermal mitigation. For example, a user equipment (UE) may transmit channel state feedback (CSF) with a report of a first rank that is less than a second rank associated with a channel condition and may communicate with a base station using a configuration associated with the first rank and without a set of sounding reference signals (SRSs). Alternatively, the UE may transmit one or more SRSs using a configuration associated with the first rank. In this way, by refraining from transmission of the SRSs or by adjusting the configuration the SRSs, the UE causes the base station to support downlink throttling.