Patents by Inventor Hao Hsu

Hao Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240078342
    Abstract: Examples described herein relate to a security management system to secure a container ecosystem. In some examples, the security management system may protect one or more entities such as container management applications, container images, containers, and/or executable applications within the containers. The security management system may make use of digital cryptography to generate digital signatures corresponding to one or more of these entities and verify them during the execution so that any compromised entities can be blocked from execution and the container ecosystem may be safeguarded from any malicious network attacks.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 7, 2024
    Inventors: Wan-Yen Hsu, Chih-Hao Chang, Lin-Chan Hsiao
  • Publication number: 20240078344
    Abstract: Examples described herein relate to a security management system to secure a container ecosystem. In some examples, the security management system may protect one or more entities such as container management applications, container images, containers, and/or executable applications within the containers. The security management system may make use of digital cryptography to generate digital signatures corresponding to one or more of these entities and verify them during the execution so that any compromised entities can be blocked from execution and the container ecosystem may be safeguarded from any malicious network attacks.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Inventors: Wan-Yen Hsu, Chih-Hao Chang, Lin-Chan Hsiao
  • Patent number: 11923396
    Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wei Hsu, Tsai-Hao Hung, Chung-Yu Lin, Ying-Hsun Chen
  • Patent number: 11920238
    Abstract: A method of making a sealing article that includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Peng-Cheng Hong, Jun-Liang Pu, W. L. Hsu, Chung-Hao Kao, Chia-Chun Hung, Cheng-Yi Wu, Chin-Szu Lee
  • Publication number: 20240071535
    Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.
    Type: Application
    Filed: October 16, 2022
    Publication date: February 29, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chung-Hao Chen, Chi-Hsiu Hsu, Chi-Fa Lien, Ying-Ting Lin, Cheng-Hsiao Lai, Ya-Nan Mou
  • Publication number: 20240071825
    Abstract: Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Tin-Hao Kuo, Che-Wei Hsu
  • Patent number: 11915746
    Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang, Cheng Hung Lee
  • Patent number: 11913876
    Abstract: An optical water-quality detection apparatus includes a detection device, a biofilm-inhibition light source, a detection light source and a sensor. The detection device includes a detection chamber. The biofilm-inhibition light source is disposed outside the detection chamber and configured to emit biofilm-inhibition light. The detection light source is disposed outside the detection chamber and configured to emit detection light. The sensor is configured to sense the detection light penetrating the detection chamber. A beam of the detection light and a beam of the inhibition light overlaps as penetrating the detection chamber.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: February 27, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Jung Chang, Jui-Hung Tsai, Ying-Hao Wang, Chih-Hao Hsu
  • Patent number: 11915979
    Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei Ying Lai, Chia-Wei Hsu, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
  • Patent number: 11907027
    Abstract: A portable information handling system supports a flexible OLED display film over housing portions rotationally coupled by a hinge by folding the OLED display film over the hinge. Hinge brackets that couple to the housing portions each have a gear member with a semicircular shape gear inner circumference that engages a gear subassembly of the hinge main body. Hinge bracket rotation translates through the gear subassembly for synchronized housing rotation. The hinge main body has first and second semicircular portions with a smooth surface defined to accept the outer circumference smooth surface of the gear member semicircular shape at first and second rotation axes about which the hinge brackets pivot so that the display film has space to fold in the closed position.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: February 20, 2024
    Assignee: Dell Products L.P.
    Inventors: Christopher A. Torres, Kevin M. Turchin, Enoch Chen, Anthony J. Sanchez, Kai-Cheng Chao, Chia-Hao Hsu, Chia-Huang Chan
  • Patent number: 11908683
    Abstract: The present application discloses a manufacturing method of a silicon nitride thin film, a thin film transistor and a display panel, the method includes following steps: providing a silane precursor into an atomic layer deposition apparatus for a preset time period, and remaining the silane precursor for a preset time period after the provision; providing an inert gas into the atomic layer deposition apparatus for a preset time period for the first time, and purging the silane precursor; providing a nitrogen supplying precursor into the atomic layer deposition apparatus for a preset time period, and remaining the nitrogen supplying precursor for a preset time period after the provision; providing the inert gas into the atomic layer deposition apparatus for a preset time period for the second time, and purging the nitrogen supplying precursor; repeating for a preset number of times the steps of providing the silane precursor, providing the inert gas for the first time, providing the nitrogen supplying precurso
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: February 20, 2024
    Assignees: BEIHAI HKC OPTOELECTRONICS TECHNOLOGY CO., LTD., HKC CORPORATION LIMITED
    Inventors: En-Tsung Cho, Wanfei Yong, Je-Hao Hsu, Yuming Xia, Haijiang Yuan
  • Patent number: 11908767
    Abstract: A semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: February 20, 2024
    Assignee: MEDIATEK INC.
    Inventors: Che-Hung Kuo, Hsing-Chih Liu, Chia-Hao Hsu
  • Publication number: 20240053676
    Abstract: A method includes performing a lithography process using a mask and a pellicle membrane; detaching the pellicle membrane from the mask after the lithography process is completed; performing an inspection process to the pellicle membrane, the inspection process including generating a laser beam toward the pellicle membrane from a laser source, such that the laser beam passes through the pellicle membrane; and generating an image by receiving the laser beam passing through the pellicle membrane using an image sensor; and determining whether a particle is present on the pellicle membrane or a pin hole is present in the pellicle membrane based on the image.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia Hao CHANG, Pei-Cheng HSU, Chih-Cheng CHEN, Huan-Ling LEE, Ting-Hao HSU, Hsin-Chang LEE
  • Publication number: 20240051349
    Abstract: A structure for enhancing sidewall marking contrast and tire with the same are disclosed. The structure includes a plurality of structural units each having at least three quadrilaterals extending outward radiatively from a center thereof so that the structural unit form a code on a sidewall of a tire. The structure enhances sidewall marking contrast and increase observability of the code against the sidewall, thereby helping impress consumers with accentuated product distinctiveness and/or brand image.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 15, 2024
    Inventors: MIN-CHI LIN, YU-HAO HSU, CHANG-CHIH CHANG, THI KIM CHI DUONG
  • Patent number: 11901394
    Abstract: The present application discloses a display panel and a manufacturing method therefor, and the method includes steps of: forming a photosensitive element layer, forming a light collimating layer on the photosensitive element layer, and forming an active light-emitting matrix layer on the light collimating layer; where the step of forming the light collimating layer includes: providing a metal substrate, putting the metal substrate into an electrolyte, and preparing a porous oxidized metal as the light collimating layer by a two-step oxidation method.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: February 13, 2024
    Assignees: BEIHAI HKC OPTOELECTRONICS TECHNOLOGY CO., LTD., HKC CORPORATION LIMITED
    Inventors: En-Tsung Cho, Jie Ding, Je-Hao Hsu, Lidan Ye
  • Publication number: 20240042712
    Abstract: An optical element and a method for manufacturing the optical element are described. The optical element includes a transparent substrate, an optical layer, and an adhesive layer. The optical layer is located on a surface of the transparent substrate. The optical layer has a first surface and a second surface, which are opposite to each other. The first surface is set with various diffracting optical structures. A refractive index of the optical layer is equal to or greater than 1.4. The adhesive layer is sandwiched between the surface of the transparent substrate and the second surface of the optical layer.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Inventors: Han Yi KUO, Shu-Hao HSU, Yin Tung LU
  • Publication number: 20240045104
    Abstract: An optical element and a method for manufacturing the optical element are described. The optical element includes a light penetrating substrate, an optical layer, and an adhesive layer. The optical layer is located on a surface of the light penetrating substrate. The optical layer has a first surface and a second surface, which are opposite to each other. The first surface is set with various diffracting optical structures. A refractive index of the optical layer is ranging from substantially 1 to substantially 4. The adhesive layer is sandwiched between the surface of the light penetrating substrate and the second surface of the optical layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: February 8, 2024
    Inventors: Han Yi KUO, Shu-Hao HSU, Yin Tung LU
  • Publication number: 20240043643
    Abstract: A medical device include a polyurethane layer and a hydro-specific layer that is covalently bonded to the polyurethane layer. The polyurethane layer may include a plurality of monomer residues, at least some of which include pendent alkene groups. The hydro-specific layer may be a hydrophilic layer or a hydrophobic layer depending on the specific molecules used to form the hydro-specific layer. As an example, the hydro-specific layer may be covalently bonded to the polyurethane layer via a thiol-ene or alkene hydrothiolation reaction between the plurality of pendent alkene groups and a plurality of thiol-terminated hydro-specific molecules forming the hydro-specific layer.
    Type: Application
    Filed: July 13, 2023
    Publication date: February 8, 2024
    Applicant: BOSTON SCIENTIFIC SCIMED, INC.
    Inventors: Yen-Hao Hsu, Joseph Thomas Delaney, Paul Vincent Grosso, Patrick Willoughby
  • Patent number: 11886065
    Abstract: The present disclosure relates to a display panel, a temperature compensation method thereof and a display device. The display panel includes: a first substrate; a second substrate; a liquid crystal layer; a plurality of temperature sensors; a plurality of heaters; an electrical signal supply circuit; a processor; and a controller. The display device includes a driving circuit and the display panel. The driving circuit includes a source driving circuit, a gate driving circuit, and a timing controller.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: January 30, 2024
    Assignees: BEIHAI HKC OPTOELECTRONICS TECHNOLOGY CO., LTD., CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Kaijun Liu, Yu Lien Chou, Je-Hao Hsu
  • Patent number: D1014421
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: February 13, 2024
    Assignee: Cheng Shin Rubber Industrial Co., Ltd.
    Inventors: Min-Chi Lin, Yi-Ta Lu, Yi-Zhen Huang, Qi-Zhi Zhan, Jyun De Li, Yu-Hao Hsu, Jyun-Yi Ke