Patents by Inventor Hao Hsu

Hao Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240161381
    Abstract: A computer-executable method for generating a side-by-side three-dimensional (3D) image includes the steps of creating a 3D mesh and estimating depth information of the raw image. The method further includes the steps of updating the left mesh area and the right mesh area of the 3D mesh based on the estimated depth information of the raw image and projecting each of the mesh vertices of the left mesh area onto a coordinate system of the side-by-side 3D image based on a left eye position, and projecting each of the mesh vertices of the right mesh area onto the coordinate system of the side-by-side 3D image based on a right eye position. The method further obtains the side-by-side 3D image by coloring the left mesh area and the right mesh area projected onto the coordinate system of the side-by-side 3D image based on the raw image.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 16, 2024
    Inventors: Sergio CANTERO CLARES, Wen-Cheng HSU, Shih-Hao LIN, Chih-Haw TAN
  • Publication number: 20240161822
    Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 16, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang, Cheng Hung Lee
  • Publication number: 20240163062
    Abstract: Methods, apparatuses, and computer-readable medium are provided for rate matching. An example method may include receiving a rate matching pattern configuration indicating at least a first control resource set (CORESET) in a first bandwidth part (BWP) and a second CORESET in a second BWP. The example method may also include receiving a physical downlink shared channel (PDSCH) in the first BWP. The example method may include processing the PDSCH transmission based on the rate matching pattern configuration, where the processing may include rate matching around resources of the first CORESET and first associated search space (SS) sets and the second CORESET and second associated SS sets.
    Type: Application
    Filed: May 17, 2022
    Publication date: May 16, 2024
    Inventors: Kazuki TAKEDA, Peter GAAL, Hobin KIM, Andrew CHEN, Chun-Hao HSU, Huilin XU, Harinath Reddy PATEL, Pankaj Shivcharan GUPTA, Ashutosh GUPTA, Neeraj PANWAR
  • Publication number: 20240153823
    Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Inventors: Pei Ying Lai, Chia-Wei Hsu, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
  • Publication number: 20240153757
    Abstract: A manufacturing method of a silicon nitride thin film, a thin film transistor, and a display panel are disclosed, the method including: providing a silane precursor into an atomic layer deposition apparatus for a preset time period, and remaining the silane precursor for a preset time period; providing an inert gas thereinto for a preset time period for the first time, and purging the silane precursor; providing a nitrogen supplying precursor for a preset time period, and remaining the nitrogen supplying precursor for a preset time period; providing the inert gas for a preset time period for the second time, and purging the nitrogen supplying precursor; repeating for a preset number of times the steps of providing the silane precursor, providing the inert gas for the first time, providing the nitrogen supplying precursor and providing the inert gas for the second time to form the silicon nitride thin film.
    Type: Application
    Filed: January 15, 2024
    Publication date: May 9, 2024
    Inventors: En-Tsung CHO, Wanfei YONG, Je-Hao HSU, Yuming XIA, Haijiang YUAN
  • Publication number: 20240154943
    Abstract: Apparatus, systems, and methods a crypto chat social software system can use the user's biological information to ensure the security of the account through a secure encryption method, which is not easy to be cracked, so that the user can fully control the security of his account. Encryption on each data generated by the user's application of social chat software is performed to ensure that only the users themselves can view the application's data and digital assets. The server storage can be decentralized in that al data stored and backed up are encrypted information. Accordingly, users' private data and digital assets cannot be stolen and abused. At the same time, the user's data will not be affected, the user still owns, and only the user owns their private data and digital assets.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Inventors: Ye Zhao, Shihao Li, Han Qin, Zhen Sun, Hao Hsu, Jiayang Qin
  • Patent number: 11977251
    Abstract: A backlight module including a light guide plate, a light source, an upper prism sheet, and a lower prism sheet is provided. The light guide plate has a light incident surface and a light emitting surface. The upper prism sheet is disposed at a side of the light emitting surface of the light guide plate. The upper prism sheet includes an upper substrate and first prism microstructures. Cross-sections of the first prism microstructures are isosceles triangles, and apex angles thereof fall within a range of 80 to 90 degrees. The lower prism sheet is disposed between the light guide plate and the upper prism sheet. The lower prism sheet includes a lower substrate and second prism microstructures. Cross-sections of the second prism microstructures are isosceles triangles, and apex angles thereof fall within a range of 100 to 130 degrees.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: May 7, 2024
    Assignee: Coretronic Corporation
    Inventors: Chun-Hsiang Hsu, Yen-Hao Lin, Wei-Hsuan Cheng
  • Patent number: 11978802
    Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Wei Hsu, Chih-Hao Wang, Huan-Chieh Su, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu
  • Patent number: 11978714
    Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
  • Publication number: 20240145470
    Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Lung-Kun CHU, Mao-Lin HUANG, Chung-Wei HSU, Jia-Ni YU, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20240146377
    Abstract: This disclosure provides systems, methods and apparatuses for enabling downlink throttling, such as for thermal mitigation. For example, a user equipment (UE) may transmit channel state feedback (CSF) with a report of a first rank that is less than a second rank associated with a channel condition and may communicate with a base station using a configuration associated with the first rank and without a set of sounding reference signals (SRSs). Alternatively, the UE may transmit one or more SRSs using a configuration associated with the first rank. In this way, by refraining from transmission of the SRSs or by adjusting the configuration the SRSs, the UE causes the base station to support downlink throttling.
    Type: Application
    Filed: December 1, 2021
    Publication date: May 2, 2024
    Inventors: James Francis GEEKIE, Alexei Yurievitch GOROKHOV, Chun-Hao HSU, Mahbod GHELICHI, Sivaram Srivenkata PALAKODETY, Pranay Sudeep RUNGTA, Krishna Chaitanya MUKKERA, Adarsh Kumar JINNU
  • Publication number: 20240142664
    Abstract: Two types of blue light blocking contact lenses are provided and are formed by curing different compositions. The first composition includes a blue light blocking component formed by mixing or reacting a first hydrophilic monomer and a yellow dye, a first colored dye component formed by mixing or reacting a second hydrophilic monomer and a first colored dye, at least one third hydrophilic monomer, a crosslinker, and an initiator. The first colored dye includes a green dye, a cyan dye, a blue dye, an orange dye, a red dye, a black dye, or combinations thereof. The second composition includes a blue light blocking component, at least one hydrophilic monomer, a crosslinker, and an initiator. The blue light blocking component is formed by mixing or reacting glycerol monomethacrylate and a yellow dye. Further, methods for preparing the above contact lenses are provided.
    Type: Application
    Filed: February 12, 2023
    Publication date: May 2, 2024
    Inventors: Han-Yi CHANG, Chun-Han CHEN, Tsung-Kao HSU, Wei-che WANG, Yu-Hung LIN, Wan-Ying GAO, Li-Hao LIU
  • Publication number: 20240143455
    Abstract: A virtual machine backup method, performed by a first host, includes: capturing a request to write data from a virtual machine to a hard disk image file, wherein the request includes written data and input and output location information, copying the written data to a temporary storage area, calculating a first key of the written data, storing the first key, the input and output location information into a first resource location structure, pausing an operation of the virtual machine and generating a second resource location structure according to the first resource location structure, the first key and a second key, and outputting a backup data set to a second host according to the second resource location structure, wherein the backup data set includes the second resource location structure and only one of existing data and the written data when the first key and the second key are the same.
    Type: Application
    Filed: May 15, 2023
    Publication date: May 2, 2024
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Lee Chung CHEN, Li Hao CHIANG, Gin CHI, Wei Jie HSU, Jiann Wen WANG, Wen Dwo HWANG
  • Publication number: 20240145919
    Abstract: An antenna module includes a first metal plate and a frame body. The frame body surrounds the first metal plate. The frame body includes a first antenna radiator, a second antenna radiator, a third antenna radiator, a first breakpoint and a second breakpoint. The first antenna radiator includes a first feeding end and excites a first frequency band. The second antenna radiator includes a second feeding end and excites a second frequency band. The third antenna radiator includes a third feeding end and excites a third frequency band. The first breakpoint is located between the first antenna radiator and the second antenna radiator. The second breakpoint is located between the second antenna radiator and the third antenna radiator. An electronic device including the above-mentioned antenna module is also provided.
    Type: Application
    Filed: September 6, 2023
    Publication date: May 2, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Shih-Keng Huang, Chao-Hsu Wu, Chih-Wei Liao, Sheng-Chin Hsu, Hao-Hsiang Yang, Tse-Hsuan Wang
  • Publication number: 20240143053
    Abstract: A mainboard device and an update method of the basic input-output system thereof are provided. The mainboard device includes a flash memory, a universal serial bus (USB) port, and a microprocessor. The code of the basic input-output system is stored in the flash memory. The USB port is connected to an external USB device, wherein the external USB device includes a supply power and stores an update code. The microprocessor includes a power-switching device coupled to the system power and the USB port. When the power-switching device detects that the system power does not provide power and the USB port is provided with the supply power, the microprocessor provides power to the flash memory based on the supply power, and the microprocessor accesses the update code of the external USB device to perform an update operation on the code in the flash memory.
    Type: Application
    Filed: September 22, 2023
    Publication date: May 2, 2024
    Inventors: Keng Hao Hsu, Che Min Liao
  • Publication number: 20240145379
    Abstract: Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.
    Type: Application
    Filed: February 23, 2023
    Publication date: May 2, 2024
    Inventors: Yen-Kun Lai, Wei-Hsiang Tu, Ching-Ho Cheng, Cheng-Nan Lin, Chiang-Jui Chu, Chien Hao Hsu, Kuo-Chin Chang, Mirng-Ji Lii
  • Publication number: 20240137483
    Abstract: An exemplary embodiment of the invention provides an image processing method for a virtual reality display system. The method includes: enabling a first shared buffer and a second shared buffer; performing an image capturing operation to obtain a first image from a virtual reality scene; storing the first image to the first shared buffer; in response to that the storing of the first image is finished, reading the first image from the first shared buffer; performing a depth estimation operation on the first image to obtain depth information corresponding to the first image; storing the depth information to the second shared buffer; in response to that the storing of the depth information is finished, reading the depth information from the second shared buffer; performing an image generation operation according to the depth information to generate a pair of second images corresponding to the virtual reality scene; and outputting the pair of second images by a display of the virtual reality display system.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Applicant: Acer Incorporated
    Inventors: Sergio Cantero Clares, Wen-Cheng Hsu, Shih-Hao Lin, Chih-Haw Tan
  • Publication number: 20240130714
    Abstract: Disclosed are computer-implemented or computer-aided method for diagnosing or predicting the risk of obstructive sleep apnea in a subject. The methods comprise determining whether the subject has obstructive sleep apnea based on at least one quantitative ultrasound parameter and/or at least one morphometric parameter.
    Type: Application
    Filed: May 16, 2023
    Publication date: April 25, 2024
    Applicant: AMCAD BIOMED CORPORATION
    Inventors: Argon CHEN, Yi-li LEE, Pei-Yu CHAO, Wei-Hao CHEN, Wei-Yu HSU
  • Patent number: 11967570
    Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: April 23, 2024
    Assignee: MediaTek Inc.
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
  • Patent number: D1025864
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: May 7, 2024
    Assignee: Foxtron Vehicle Technologies Co., Ltd.
    Inventors: Tse-Min Cheng, Lu-Han Lee, Chia-Hao Hsu