Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: According to one aspect of the present disclosure, a memory system is provided. The memory system may include at least one non-volatile memory device and a memory controller coupled to the at least one non-volatile memory device. A multi-level mapping table may be stored in the memory device. The multi-level mapping table may be configured to implement mapping from a logical address to a physical address. The memory controller may include a buffer. A portion of the multi-level mapping table may be stored in the buffer. The memory controller may be configured to perform a random read operation on the data stored in the memory device. In response to a random read range corresponding to the random read operation meeting a preset condition, the memory controller may be configured to adjust capacity for storing different levels of mapping tables in the buffer.

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: Methods and systems for managing power of a hybrid vehicle that includes a fuel cell and a traction battery are described. In one example, cooling of the battery and fuel cell may be adjusted preemptively before the hybrid vehicle reaches high load conditions to extend fuel cell durability over its life span, meanwhile the hybrid vehicle may meet driver demand for a longer period of time while operating at the high load and high ambient temperature conditions.

Abstract: Provided are a ventilator and a vehicle having the ventilator. The ventilator includes a housing assembly, a fan blade, a first drive device, a cover plate assembly, an air guide sleeve, and a controller. The housing assembly has a first accommodation space and a vent. The fan blade and the first drive device are mounted in the first accommodation space. The first drive device is configured to drive the fan blade to rotate about a rotation axis of the fan blade, and is electrically connected to the controller. The cover plate assembly is provided at a side of the housing assembly. The air guide sleeve is provided between the cover plate assembly and the housing assembly and configured to be lifted or lowered relative to the housing assembly to expose or cover the vent. A second accommodation space is defined by the air guide sleeve and the cover plate assembly.

Abstract: Techniques for data transmission involve obtaining respective data transmission characteristics of a set of to-be-processed data transmission jobs, the data transmission characteristics of each data transmission job indicating at least one of an expected transmission time and a data size of the data transmission job; determining corresponding weights of the set of data transmission jobs based on the data transmission characteristics of the set of data transmission jobs; and determining a transmission rate of each data transmission job based on the weights and a total transmission rate used for the set of data transmission. Accordingly, different transmission rates may be assigned to different data transmission jobs, thereby increasing a recovery point objective (RPO) completion rate before a failure occurs.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: A semiconductor device includes first and second semiconductive fins, a first dielectric layer, a first gate structure, a spacer layer, and an oxide material. The first dielectric layer is laterally between the first and second semiconductive fins. From a cross-sectional view taken along a direction perpendicular to a lengthwise direction of the first semiconductive fin, the first dielectric layer has a U-shaped profile. The first gate structure extends across the first and second semiconductive fins and the first dielectric layer. The spacer layer underlies the first dielectric layer and further extends to laterally surround a lower portion of the first dielectric layer, a lower portion of the first semiconductive fin, and a lower portion of the second semiconductive fin. The oxide material is nested in the first dielectric layer. A top surface of the oxide material is at an elevation higher than a top surface of the spacer layer.

Abstract: Embodiments of the present application disclose a photonic chip, a LiDAR, and a mobile device. The photonic chip has a substrate, a cladding layer, a first coupler, a first beam splitter, an emitting waveguide module, and a first optical adjusting monitoring module. The first beam splitter includes a first port, a second port, a third port, and a fourth port. The first beam splitter is configured to output the optical signal input through the first port through the third port and the fourth port, and to output the optical signal input through the third port through the first port and the second port. The first optical adjusting monitoring module includes a first photodetector. Monitors the optical power of the return light received by the emitting waveguide module through the first optical adjusting monitoring module integrated on the photonic chip, making the process more time-saving and labor-saving.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures and a gate stack wrapped around the semiconductor nanostructures. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching one or more of the semiconductor nanostructures. The semiconductor device structure further includes an isolation structure continuously extending across edges of the semiconductor nanostructures.

Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer, wherein the first gate spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface of the first gate spacer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: A temperature-pressure sensor includes a shell, a pressure sensitive component provided in the shell and a temperature sensitive component provided in the lower cavity. The shell is provided with a fluid inlet. The pressure sensitive component includes a ceramic plate laterally extended. The temperature sensitive component includes a temperature sensor, and two connection ends of the temperature sensor are respectively electrically connected to the circuit board through an elastic connection body, a conductive pin and a conductor. The conductive pin is respectively correspondingly penetrated through two via holes opened on the ceramic plate, and a gap between the conductive pin and the corresponding via hole is sealed by a seal body made of glass material; and the fluid inlet is communicated with the lower cavity.

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.

Abstract: A semiconductor structure includes a source/drain (S/D) region, one or more dielectric layers over the S/D region, one or more semiconductor channel layers connected to the S/D region, an isolation structure under the S/D region and the one or more semiconductor channel layers, and a via under the S/D region and electrically connected to the S/D region. A lower portion of the via is surrounded by the isolation structure and an upper portion of the via extends vertically between the S/D region and the isolation structure.

Abstract: Disclosed in the present application are a display apparatus and a processing method. According to the method, a data stream from the external device in connection with the display apparatus is received; a device information frame in the data stream is obtained, where the device information frame is a data frame generated by the external device according to a basic transmission protocol between the external device and the display apparatus; marker bits in the device information frame are traversed; in response to the external device supporting the automatic control protocol, a play mode is switched according to usage scenario information added in the data stream; and in response to the external device not supporting the automatic control protocol, a play mode is switched according to a device type of the external device.

Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.