Patents by Inventor Hao Wang

Hao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
    Publication number: 20250169093
    Abstract: A method includes forming a plurality of fin structures extending along a first direction. The method includes forming a dummy fin structure disposed between two adjacent fin structures. The dummy fin structure also extends along the first direction and includes a deformable layer. The method includes recessing portions of each fin structure. The method includes forming source/drain structures over the recessed fin structures. The method includes deforming the deformable layer of the dummy fin structure to apply either a tensile stress or a compressive stress on the source/drain structures coupled to each of the two adjacent fin structures.
    Type: Application
    Filed: January 22, 2025
    Publication date: May 22, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • COMPOUND FOR REGULATING AND CONTROLLING 15-PGDH ACTIVITY AND PREPARATION METHOD THEREFOR
    Publication number: 20250154162
    Abstract: The present application relates to a compound represented by formula (I) and used for regulating and controlling the 15-PGDH activity and an application thereof in the pharmaceutical field. The present application further provides a method for preparing the compound of the present application, a composition comprising the compound of the present application, and a pharmaceutical use of the compound in serving as a 15-PGDH inhibitor.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 15, 2025
    Inventors: Anle YANG, Sen JI, Hao WANG, Dewei ZHANG, Xiao WANG, Xinying QIAN, Zhiyong LI, Xiaodong ZHANG, Jun TANG
  • FULL-SCENE CYBERSECURITY THREAT-RELATED ANALYSIS METHOD AND SYSTEM THEREOF
    Publication number: 20250159008
    Abstract: A full-scene cybersecurity threat-related analysis method and a system thereof include: obtaining cybersecurity-related data, wherein the cybersecurity-related data includes network flow values at a plurality of predetermined time points within a predetermined time length and a network log of the predetermined time length; extracting a network flow chronological feature of the network flow values at the plurality of predetermined time points; extracting a log semantics feature of the network log; fusing the network flow chronological feature and the log semantics feature to obtain a network flow-log semantics cross-fusion feature; and determining a mode of attacker's behaviors based on the network flow-log semantics cross-fusion feature. Thus, it is possible to intelligently identify a mode of attacker's behaviors and detect a potential threat in the network.
    Type: Application
    Filed: November 10, 2024
    Publication date: May 15, 2025
    Inventors: Fangfang Dang, Lijing Yan, Shuai Li, Shaoyong Guo, Ying Yang, Dingding Li, Hao Wang, Qidi Jiao, Zhiying Wang
  • SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF
    Publication number: 20250159949
    Abstract: A semiconductor device includes nanostructures extending in a first direction above a substrate and spaced apart in a second direction perpendicular to the first direction, a gate dielectric layer wrapping around each of the nanostructures, a first p-type work function metal layer between the adjacent nanostructures, a second p-type work function metal layer in contact with opposite sidewalls of the first p-type work function metal layer and opposite sidewalls of the gate dielectric layer, and an n-type work function metal layer covering the second p-type work function metal layer. The second p-type work function metal layer comprises a main layer and a cap layer over the main layer, wherein the cap layer has a material different from a material of the main layer.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 15, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Ni YU, Lung-Kun CHU, Chung-Wei HSU, Chun-Fu LU, Shih-Hao LAI, Kuo-Cheng CHIANG, Chih-Hao WANG
  • POST-PROCESSING DIFFERENTIALLY PRIVATE SYNTHETIC DATA
    Publication number: 20250156746
    Abstract: An embodiment generates, using a probability distribution of synthetic data, a first value of a utility measure function, and a second value of the utility measure function, a value of an optimization variable, the synthetic data generated from a source dataset using a differential privacy technique, the utility measure function measuring a characteristic of a dataset. An embodiment computes, using the value of the optimization variable, a sampling weight, the sampling weight comprising a probability of selecting a portion of data from the synthetic data. An embodiment samples, according to the sampling weight, the synthetic data, the sampling resulting in a sampled synthetic dataset. An embodiment trains, using the sampled synthetic dataset, a machine learning model, the training resulting in a trained machine learning model.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 15, 2025
    Applicant: International Business Machines Corporation
    Inventors: Hao Wang, Shivchander Sudalairaj, Akash Srivastava
  • Integrated circuit structure and method with hybrid orientation for FinFET
    Patent number: 12302640
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Backside gate contact
    Patent number: 12302607
    Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.
    Type: Grant
    Filed: May 21, 2024
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Lo-Heng Chang, Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Remote switch-off mechanism and rotary switch
    Patent number: 12300447
    Abstract: A remote switch-off mechanism and a rotary switch relates to the field of electrical technologies. A housing, an energy storage component, and a tripping component are provided. The energy storage component includes a latch, an energy storage spring, a rotating shaft, and an energy storage panel connected to the rotating shaft, an abutting portion is disposed on the energy storage panel, a first end of the energy storage spring is clamped to the housing, and a second end of the energy storage spring abuts against the abutting portion. The latch includes a hinged portion hinged to the housing, a limiting portion for limiting the second end of the energy storage spring, and a tripping portion that cooperates with the tripping component, and an elastic member is disposed between the latch and the housing, so that the tripping portion has a trend of moving toward the tripping component.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: May 13, 2025
    Assignees: Huawei Digital Power Technologies Co., Ltd., Shanghai Liangxin Electrical Co., Ltd.
    Inventors: Jian Shi, Hao Wang, Wei Shi, Xiufeng Zhang, Xiaokang Tian
  • Transistor including downward extending silicide
    Patent number: 12300723
    Abstract: An integrated circuit includes a transistor having a plurality of semiconductor nanostructures arranged in a stack and corresponding to channel regions of the transistor. The transistor includes a source/drain region in contact with the channel regions. The transistor includes a silicide that extends downward along a side of the source/drain region.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Chien Cheng, Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Bo-Rong Lin, Chih-Hao Wang
  • Multigate device with air gap spacer and backside rail contact and method of fabricating thereof
    Patent number: 12300731
    Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng
  • Metal oxide interlayer structure for NFET and PFET
    Patent number: 12300739
    Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Data caching based on data popularity
    Patent number: 12299320
    Abstract: A method, apparatus, electronic device and storage medium for data caching based on data popularity is provided. In the method, first access data transmitted by at least one client is received. The first access data represents an instruction log of a remote direct data read instruction transmitted by the client for target data cached in a non-uniform memory access structure. A data popularity of the target data is obtained based on the first access data. The data popularity represents a frequency of the target data accessed by the remote direct data read instruction. Based on the data popularity of the target data, the target data is cached to a target location in a data storage unit implemented based on the non-uniform memory access structure. Alternatively, the target data out of the data storage unit is migrated. The target location has a data read-write speed corresponding to the data popularity.
    Type: Grant
    Filed: June 5, 2024
    Date of Patent: May 13, 2025
    Assignee: Beijing Volcano Engine Technology Co., Ltd.
    Inventors: Xiao Liu, Haiyang Shi, Hao Wang
  • Integrated circuit with backside trench for metal gate definition
    Patent number: 12302630
    Abstract: An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The first and second nanosheet each include gate electrodes. A gate isolation structure extends from a backside of the substrate between the gate electrodes. The gate isolation structure physically and electrically isolates the first and second gate electrodes from each other.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Jung-Chien Cheng, Shi-Ning Ju, Guan-Lin Chen, Chih-Hao Wang
  • Selective liner on backside via and method thereof
    Patent number: 12300722
    Abstract: A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap. A backside power rail is included.
    Type: Grant
    Filed: June 21, 2024
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Interconnect structure
    Patent number: 12300601
    Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary method includes receiving a workpiece including a dielectric layer and a contact via extending through the dielectric layer, selectively forming a metal feature on a top surface of the contact via, forming a barrier layer over the metal feature and the dielectric layer, wherein the contact via is spaced apart from the barrier layer, and, forming a metal fill layer over the barrier layer. The metal feature is formed of a first material and the barrier layer is formed of a second material different from the first material.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Process and structure for source/drain contacts
    Patent number: 12300727
    Abstract: A method includes providing a structure having source/drain electrodes and a first dielectric layer over the source/drain electrodes; forming a first etch mask covering a first area of the first dielectric layer; performing a first etching process to the first dielectric layer, resulting in first trenches over the source/drain electrodes; filling the first trenches with a second dielectric layer that has a different material than the first dielectric layer; removing the first etch mask; performing a second etching process including isotropic etching to the first area of the first dielectric layer, resulting in a second trench above a first one of the source/drain electrodes; depositing a metal layer into at least the second trench; and performing a chemical mechanical planarization (CMP) process to the metal layer.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Huan Jao, Lin-Yu Huang, Sheng-Tsung Wang, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
  • Structure and formation method of semiconductor device with isolation structure
    Patent number: 12300719
    Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a first fin structure and a second fin structure over a substrate. The method also includes forming a first metal gate stack wrapped around and extending across the first fin structure and the second fin structure. The method further includes forming a second metal gate stack wrapped around and extending across the first fin structure and the second fin structure. In addition, the method includes forming a protective structure extending into the first gate stack and forming a dielectric structure extending into the protective structure and the second metal gate stack. A portion of the protective structure is between the dielectric structure and the metal gate stack.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Chien Cheng, Kuo-Cheng Chiang, Shi-Ning Ju, Guan-Lin Chen, Chih-Hao Wang
  • Semiconductor device having air gap and method of fabricating thereof
    Patent number: 12300734
    Abstract: Methods and devices that provide for a fin structure and a dielectric fin structure. A gate structure is formed over the fin structure and the hybrid fin structure. A plurality of dielectric layers is adjacent the gate structure and over the hybrid fin structure between the gate structure and a contact element over the dielectric fin structure. The plurality of dielectric layers includes an air gap, formed by removal of a dummy spacer layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hao Chang, Lin-Yu Huang, Sheng-Tsung Wang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Air gap in inner spacers and methods of fabricating the same in field-effect transistors
    Patent number: 12300735
    Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate stack having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers, an inner spacer disposed on sidewalls of the bottom portion of the metal gate stack, an air gap extending in the inner spacer, and an epitaxial source/drain (S/D) feature disposed over the inner spacer and adjacent to the metal gate stack.
    Type: Grant
    Filed: May 20, 2024
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien Ning Yao, Bo-Feng Young, Chih-Hao Wang, Kuan-Lun Cheng, Sai-Hooi Yeong
  • Scanning module, distance measuring device and mobile platform
    Patent number: 12298392
    Abstract: A distance measuring device includes a scanning module including a rotor assembly, the rotor assembly including a rotor, the rotor including a receiving cavity and an optical element disposed in the receiving cavity, the optical element rotating synchronously with the rotor assembly, the optical element including a first end and a second end, the first end and the second end being respectively positioned at two ends in a radial direction of the optical element, a thickness of the first end being greater than a thickness of the second end, a notch being formed on a side of the first end of the rotor or/and the optical element; and a distance measuring module configured to emit a laser pulse to the scanning module.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: May 13, 2025
    Assignee: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Hao Wang, Huai Huang