Patents by Inventor Harmeet Singh

Harmeet Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10938694
    Abstract: A system for detecting a source or destination of abnormal message traffic on a network, the system having: an abnormality detection engine configured to track messages between a plurality of sources and a plurality of destinations; and one or more abnormality detectors configured to: determine a bandwidth variation of a rate of messages to a destination, wherein determining the bandwidth variation comprises: generate a bandwidth counter for each destination; update the bandwidth counter based on the rate of messages to a destination; determine if a predetermined amount of time has passed; and compare values in the source and destination pair counter to a predetermined source and destination pair threshold and comparing values in the bandwidth counter to a predetermined steady rate of messages after the predetermined amount of time has passed to determine if there is abnormal message traffic related to a source or destination based on both comparisons.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: March 2, 2021
    Inventors: Don Bowman, Harmeet Singh Bedi
  • Patent number: 10872748
    Abstract: An electrostatic chuck includes an embedded electrode receiving a first voltage to electrostatically attract a semiconductor substrate to the electrostatic chuck. A plurality of current loops are disposed in at least one of the electrostatic chuck and an edge ring surrounding the electrostatic chuck. The current loops are laterally spaced apart. Each current loop is a wire formed into a loop. One or more DC power sources are electrically connected to the current loops. A controller supplies the first voltage to the embedded electrode, supplies a DC current to the current loops from the power sources, and controls the power sources. Each current loop is independently operable and generates a localized DC magnetic field proximate to the semiconductor substrate on receiving the DC current during plasma processing of the semiconductor substrate to adjust the plasma processing of the semiconductor substrate. The localized DC magnetic field does not generate plasma.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: December 22, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Harmeet Singh, Keith Gaff, Brett Richardson, Sung Lee
  • Publication number: 20200372738
    Abstract: A smart lock system that includes a smart lock that electronically locks and unlocks a door and a server that outputs a command to the smart lock to lock or unlock the door via the internet in response to an instruction received via the internet from a user device. The user device may also (simultaneously) directly transmit an instruction to the smart lock (e.g., via Bluetooth). The user device may also directly transmit an instruction to the smart lock to unlock the door in response to a determination that the user device is within a predefined geofenced region around the smart lock. The smart lock may also include a keypad. The smart lock may also include a camera that captures images and output those images to the server for transmittal to the user device. The smart may also include a motion sensor and capture images in response to detected motion.
    Type: Application
    Filed: December 6, 2019
    Publication date: November 26, 2020
    Inventors: Harmeet Singh, Anand Choudha, Nayna Choudha, Jitendra Singh Phalswal
  • Patent number: 10821374
    Abstract: A mud retort assembly includes a retort that heats a fluid and thereby generates vapors, a condenser in fluid communication with the retort to at least partially condense the vapors and thereby generate a liquid, a condensate collector that receives the liquid and residual vapors via an outlet pipe of the condenser, and a collector plug having a frustoconical body that extends partially into the condensate collector at an opening to the condensate collector. The collector plug defines a central aperture that receives the outlet pipe and has an annular flange extending radially outward from the frustoconical body to rest on the condensate collector at the opening.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: November 3, 2020
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Ketan Chimanlal Bhaidasna, Richard Gary Morgan, Harmeet Singh Jammu, Andrew David Vos
  • Publication number: 20200274785
    Abstract: A system for detecting a source or destination of abnormal message traffic on a network, the system having: an abnormality detection engine configured to track messages between a plurality of sources and a plurality of destinations; and one or more abnormality detectors configured to: determine a bandwidth variation of a rate of messages to a destination, wherein determining the bandwidth variation comprises: generate a bandwidth counter for each destination; update the bandwidth counter based on the rate of messages to a destination; determine if a predetermined amount of time has passed; and compare values in the source and destination pair counter to a predetermined source and destination pair threshold and comparing values in the bandwidth counter to a predetermined steady rate of messages after the predetermined amount of time has passed to determine if there is abnormal message traffic related to a source or destination based on both comparisons.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Don BOWMAN, Harmeet Singh BEDI
  • Publication number: 20200250286
    Abstract: Systems and methods for authenticating a user using an interactive voice response application. The method includes receiving data representing a spoken voice utterance corresponding to a user of an interactive voice response application. The method further includes processing the data representing the spoken voice utterance based on a length and a quality of the spoken voice utterance. The method also includes comparing the processed data representing the spoken voice utterance and a voiceprint associated with the user. The method further includes generating a security token in response to determining that the processed data representing the spoken voice utterance substantially matches the voiceprint associated with the user. The method also includes receiving the security token from the interactive voice application and validating the security token corresponding to the user in response to determining that the security token matches a security token generated by a server computing device.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 6, 2020
    Inventors: Harmeet Singh, Robert Gage, David Marteney, Kevin Johnson
  • Publication number: 20200250287
    Abstract: Systems and methods for authenticating a user using a voice activated device. The method includes receiving first data representing a user identifier corresponding to a user and second data representing a device identifier corresponding to the voice activated device. The method further includes determining user metadata corresponding to the user identifier and a device audio type corresponding to the device identifier. The method also includes calculating a risk score based on the user metadata. The method further includes calculating a length of spoken voice utterance based on the calculated risk score. The method also includes receiving and processing third data representing a spoken voice utterance having the calculated length corresponding to the user using the voice activated device. The method further includes validating the user in response to determining that the processed third data substantially matches the voiceprint associated with the user.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 6, 2020
    Inventors: Harmeet Singh, Robert Gage, David Marteney, Kevin Johnson
  • Patent number: 10720346
    Abstract: A substrate support in a semiconductor plasma processing apparatus, comprises multiple independently controllable thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the thermal zones. A substrate support in which the substrate support is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the substrate support include bonding together ceramic or polymer sheets having thermal zones, power supply lines, power return lines and vias.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: July 21, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Harmeet Singh, Keith Gaff, Neil Benjamin, Keith Comendant
  • Publication number: 20200161139
    Abstract: Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to prevent feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate.
    Type: Application
    Filed: November 21, 2019
    Publication date: May 21, 2020
    Inventors: Keren Jacobs Kanarik, Jeffrey Marks, Harmeet Singh, Samantha Tan, Alexander Kabansky, Wenbing Yang, Taeseung Kim, Dennis M. Hausmann, Thorsten Lill
  • Patent number: 10636625
    Abstract: A plasma processing system for processing semiconductor substrates is provided. The plasma processing system includes a plasma processing volume having a volume less than the processing chamber. The plasma processing volume is defined by a top electrode, a substrate support surface opposing the surface of the top electrode and a plasma confinement structure including at least one outlet port. A conductance control structure is movably disposed proximate to the at least one outlet port and capable of controlling an outlet flow through the at least one outlet port between a first flow rate and a second flow rate. The conductance control structure controls the outlet flow rate and an at least one RF source is modulated and at least one process gas flow rate is modulated corresponding to a selected processing state set by the controller during a plasma process.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: April 28, 2020
    Assignee: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Harmeet Singh
  • Publication number: 20200110859
    Abstract: An account server receives from a user terminal an access request message containing an account identifier. A security question is retrieved from an accounts database. An authentication query message containing the security question is communicated toward the user terminal. A registered text counting rule that is associated with the account identifier is retrieved from the accounts database. Text of the security question is processed using the registered text counting rule to generate a computed security number. An authentication response message containing an answer from the user to the security question is received. A determination is made whether the answer from the user matches the computed security number. The operations selectively allow electronic access by the user terminal to information stored in a data structure associated with the account identifier within the accounts database, based on whether the answer contained in the authentication response message matches the computed security number.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 9, 2020
    Applicant: CA, Inc.
    Inventors: Vijay Shashikant Kulkarni, Lyju Vadassery, Vikrant Nandakumar, Harmeet Singh Gujral
  • Publication number: 20200110879
    Abstract: A trusted computing environment may be dynamically certified by providing a selectable boot option that controls running a loadable boot image in one of a test mode and a production mode. The test mode may automate running a processing standard validation test to obtain a processing standard validation test result. Responsive to running the processing standard validation test with a successful test result, a record indicating the successful test result and the loadable boot image is stored within the trusted computing environment, utilizing a certification process. Responsive to running the production mode, the trusted computing environment and the loadable boot image may be loaded.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Inventors: Jeb R. Linton, Warren W. Grunbok, Harmeet Singh
  • Patent number: 10586256
    Abstract: A computer-implemented method is provided for facilitating live communication between a potential customer and an enterprise in relation to a product. The method includes causing to display, by a computing device on a webpage over a communications network, an interactive banner located on the webpage that includes advertisement content related to the product. The advertisement content includes an offer to the potential customer to communicate live with the enterprise about the product. The method includes adding to the context information, by the computing device, information related to an interaction over the communications network between the potential customer and the interactive banner. The method further includes adjusting, by the computing device over the communications network, the advertisement content in the interactive banner on the webpage if the potential customer accepts the offer.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: March 10, 2020
    Assignee: FMR LLC
    Inventors: Harmeet Singh, Carsten Miller
  • Patent number: 10585347
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 10, 2020
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Richard Wise, Harmeet Singh, Alex Paterson, Andrew D. Bailey, III, Vahid Vahedi, Richard A. Gottscho
  • Publication number: 20200074442
    Abstract: A transaction authorization server receives an optical machine-readable code (OMRC) request message from a merchant terminal, which includes a transaction reference number, a transaction time, a transaction amount, and a merchant identifier associated with the merchant terminal. OMRC information is generated based on a combination of the transaction reference number and the transaction time. An OMRC response message is generated containing the OMRC information and sent toward the merchant terminal. The OMRC information is stored in a data structure with an association to the merchant identifier. An OMRC verification message is received from a user terminal, and is selectively validated based on the OMRC information that was stored. When validated, the server sends to the user terminal an OMRC validation message containing an indication that the decoded OMRC information is valid, the transaction amount, and the merchant identifier.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Applicant: CA, Inc.
    Inventors: Vijay Shashikant Kulkarni, Lyju Vadassery, Vikrant Nandakumar, Harmeet Singh Gujral
  • Patent number: 10568163
    Abstract: Described herein is a method of detecting fault conditions in a multiplexed multi-heater-zone heating plate for a substrate support assembly used to support a semiconductor substrate in a semiconductor processing apparatus.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: February 18, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventor: Harmeet Singh
  • Patent number: 10554384
    Abstract: In some embodiments, an encryption system secures data using a homomorphic encryption. The encryption system encrypts a number by encrypting a number identifier of the number and combining the number and the encrypted number identifier using a mathematical operation to generate an encrypted number. The encrypted numbers may be stored at a server system along with their number identifiers. The server system can then generate an aggregation (e.g., sum) of the encrypted numbers and provide the aggregation, the encrypted numbers, and the number identifiers. The encryption system can then separate the aggregation of the numbers from the aggregation of the encrypted numbers using an inverse of the mathematical operation used in the encryption to effect removal of an aggregation of the encrypted number identifiers of the numbers from the aggregation of the encrypted numbers. The separated aggregation of the numbers is an aggregation of the plurality of the numbers.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: February 4, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ranjita Bhagwan, Nishanth Chandran, Ramachandran Ramjee, Harmeet Singh, Antonios Papadimitriou, Saikrishna Badrinarayanan
  • Patent number: 10515816
    Abstract: Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to prevent feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 24, 2019
    Assignee: Lam Research Corporation
    Inventors: Keren Jacobs Kanarik, Jeffrey Marks, Harmeet Singh, Samantha SiamHwa Tan, Alexander Kabansky, Wenbing Yang, Taeseung Kim, Dennis M. Hausmann, Thorsten Lill
  • Publication number: 20190371576
    Abstract: An electrostatic chuck includes an embedded electrode receiving a first voltage to electrostatically attract a semiconductor substrate to the electrostatic chuck. A plurality of current loops are disposed in at least one of the electrostatic chuck and an edge ring surrounding the electrostatic chuck. The current loops are laterally spaced apart. Each current loop is a wire formed into a loop. One or more DC power sources are electrically connected to the current loops. A controller supplies the first voltage to the embedded electrode, supplies a DC current to the current loops from the power sources, and controls the power sources. Each current loop is independently operable and generates a localized DC magnetic field proximate to the semiconductor substrate on receiving the DC current during plasma processing of the semiconductor substrate to adjust the plasma processing of the semiconductor substrate. The localized DC magnetic field does not generate plasma.
    Type: Application
    Filed: July 9, 2019
    Publication date: December 5, 2019
    Inventors: Harmeet SINGH, Keith GAFF, Brett RICHARDSON, Sung LEE
  • Patent number: D912492
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 9, 2021
    Assignee: Altro Smart Inc.
    Inventors: Harmeet Singh, Anand Choudha, Nayna Choudha, Jitendra Singh Phalswal