Patents by Inventor Harmeet Singh

Harmeet Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180294140
    Abstract: A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.
    Type: Application
    Filed: June 5, 2018
    Publication date: October 11, 2018
    Inventors: John C. Valcore, JR., Harmeet Singh, Bradford J. Lyndaker
  • Publication number: 20180240686
    Abstract: A semiconductor substrate processing system includes a chamber that includes a processing region and a substrate support. The system includes a top plate assembly disposed within the chamber above the substrate support. The top plate assembly includes first and second sets of plasma microchambers each formed into the lower surface of the top plate assembly. A first network of gas supply channels are formed through the top plate assembly to flow a first process gas to the first set of plasma microchambers to be transformed into a first plasma. A set of exhaust channels are formed through the top plate assembly. The second set of plasma microchambers are formed inside the set of exhaust channels. A second network of gas supply channels are formed through the top plate assembly to flow a second process gas to the second set of plasma microchambers to be transformed into a second plasma.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 23, 2018
    Inventors: John Patrick Holland, Peter L.G. Ventzek, Harmeet Singh, Richard Gottscho
  • Patent number: 10056225
    Abstract: A plasma etching system having a substrate support assembly with multiple independently controllable heater zones. The plasma etching system is configured to control etching temperature of predetermined locations so that pre-etch and/or post-etch non-uniformity of critical device parameters can be compensated for.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 21, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Keith William Gaff, Harmeet Singh, Keith Comendant, Vahid Vahedi
  • Patent number: 10014192
    Abstract: A substrate processing system having a processing chamber for etching a layer on a substrate is provided. The system includes a chuck upon which the substrate is disposed during etching. The system also includes the chamber being divided into a plasma generating region and a substrate processing region by a separating plate structure. The system further includes a plasma source for generating plasma in the plasma generating region. The system further includes logic for introducing a first gas into the chamber, wherein the gas is suitable for etching the layer. The logic also allows the first gas to be present in the chamber for a period of time sufficient to cause adsorption of at least some of the first gas into the layer. The logic further replaces the first gas with an inert gas, generates metastables from the inert gas, and etches the layer with the metastables.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: July 3, 2018
    Assignee: Lam Research Corporation
    Inventor: Harmeet Singh
  • Patent number: 9997333
    Abstract: A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: June 12, 2018
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Harmeet Singh, Bradford J. Lyndaker
  • Publication number: 20180140968
    Abstract: A mud retort assembly includes a retort that heats a fluid and thereby generates vapors, a condenser in fluid communication with the retort to at least partially condense the vapors and thereby generate a liquid, a condensate collector that receives the liquid and residual vapors via an outlet pipe of the condenser, and a collector plug having a frustoconical body that extends partially into the condensate collector at an opening to the condensate collector. The collector plug defines a central aperture that receives the outlet pipe and has an annular flange extending radially outward from the frustoconical body to rest on the condensate collector at the opening.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Applicant: Halliburton Energy Services, Inc.
    Inventors: Ketan Chimanlal Bhaidasna, Richard Gary Morgan, Harmeet Singh Jammu, Andrew David Vos
  • Patent number: 9947557
    Abstract: A semiconductor substrate processing system includes a chamber that includes a processing region and a substrate support. The system includes a top plate assembly disposed within the chamber above the substrate support. The top plate assembly includes first and second sets of plasma microchambers each formed into the lower surface of the top plate assembly. A first network of gas supply channels are formed through the top plate assembly to flow a first process gas to the first set of plasma microchambers to be transformed into a first plasma. A set of exhaust channels are formed through the top plate assembly. The second set of plasma microchambers are formed inside the set of exhaust channels. A second network of gas supply channels are formed through the top plate assembly to flow a second process gas to the second set of plasma microchambers to be transformed into a second plasma.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 17, 2018
    Assignee: Lam Research Corporation
    Inventors: John Patrick Holland, Peter L. G. Ventzek, Harmeet Singh, Richard Gottscho
  • Publication number: 20180033596
    Abstract: A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.
    Type: Application
    Filed: October 5, 2017
    Publication date: February 1, 2018
    Inventors: John C. Valcore, Jr., Harmeet Singh, Bradford J. Lyndaker
  • Publication number: 20180033635
    Abstract: Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to prevent feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate.
    Type: Application
    Filed: September 28, 2017
    Publication date: February 1, 2018
    Inventors: Keren Jacobs Kanarik, Jeffrey Marks, Harmeet Singh, Samantha Tan, Alexander Kabansky, Wenbing Yang, Taeseung Kim, Dennis M. Hausmann, Thorsten Lill
  • Publication number: 20180012785
    Abstract: A substrate support for a substrate processing system includes a baseplate, a bond layer provided on the baseplate, and a ceramic layer arranged on the bond layer. The ceramic layer includes a first region and a second region located radially outward of the first region, the first region has a first thickness, the second region has a second thickness, and the first thickness is greater than the second thickness.
    Type: Application
    Filed: June 27, 2017
    Publication date: January 11, 2018
    Inventors: Alexander Matyushkin, John Patrick Holland, Harmeet Singh, Alexi Marakhtanov, Keith Gaff, Zhigang Chen, Fleix Kozakevich
  • Publication number: 20180005851
    Abstract: A chamber filler kit for balancing electric fields in a dielectric etch chamber is provided. A transport module filler comprises an electrical conductive body, an etch resistant surface, wherein the etch resistant surface comprises an inner curved surface, which matches a partial cylindrical bore of the etch chamber, and a wafer transport aperture, wherein the transport module filler fits into a transport aperture of the etch chamber. A transport module sealer plate is adapted to be mechanically and electrically connected to the partially cylindrical chamber body and the transport module filler. A bias housing filler is adapted to be mechanically and electrically connected to a bias housing wall and comprises a conductive body and an etch resistant surface, wherein the etch resistant surface comprises a curved surface, which matches the partial cylindrical bore.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Inventors: Benson Q. TONG, Harmeet SINGH, John HOLLAND, Ryan BISE
  • Publication number: 20170363950
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Application
    Filed: June 21, 2016
    Publication date: December 21, 2017
    Inventors: Saravanapriyan Sriraman, Richard Wise, Harmeet Singh, Alex Paterson, Andrew D. Bailey, III, Vahid Vahedi, Richard A. Gottscho
  • Patent number: 9812294
    Abstract: A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: November 7, 2017
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Harmeet Singh, Bradford J. Lyndaker
  • Patent number: 9805941
    Abstract: Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to prevent feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: October 31, 2017
    Assignee: Lam Research Corporation
    Inventors: Keren Jacobs Kanarik, Jeffrey Marks, Harmeet Singh, Samantha Tan, Alexander Kabansky, Wenbing Yang, Taeseung Kim, Dennis M. Hausmann, Thorsten Lill
  • Publication number: 20170272235
    Abstract: In some embodiments, an encryption system secures data using a homomorphic encryption. The encryption system encrypts a number by encrypting a number identifier of the number and combining the number and the encrypted number identifier using a mathematical operation to generate an encrypted number. The encrypted numbers may be stored at a server system along with their number identifiers. The server system can then generate an aggregation (e.g., sum) of the encrypted numbers and provide the aggregation, the encrypted numbers, and the number identifiers. The encryption system can then separate the aggregation of the numbers from the aggregation of the encrypted numbers using an inverse of the mathematical operation used in the encryption to effect removal of an aggregation of the encrypted number identifiers of the numbers from the aggregation of the encrypted numbers. The separated aggregation of the numbers is an aggregation of the plurality of the numbers.
    Type: Application
    Filed: January 13, 2017
    Publication date: September 21, 2017
    Inventors: Ranjita Bhagwan, Nishanth Chandran, Ramachandran Ramjee, Harmeet Singh, Antonios Papadimitriou, Saikrishna Badrinarayanan
  • Publication number: 20170229327
    Abstract: A substrate support is provided, is configured to support a substrate in a plasma processing chamber, and includes first, second and third insulative layers, conduits and leads. The first insulative layer includes heater zones arranged in rows and columns. The second insulative layer includes conductive vias. First ends of the conductive vias are connected respectively to the heater zones. Second ends of the conductive vias are connected respectively to power supply lines. The third insulative layer includes power return lines. The conduits extend through the second insulative layer and into the third insulative layer. The leads extend through the conduits and connect to the heater zones. The heater zones are connected to the power return lines by the leads and are configured to heat corresponding portions of the substrate to provide a predetermined temperature profile across the substrate during processing of the substrate in the plasma processing chamber.
    Type: Application
    Filed: April 26, 2017
    Publication date: August 10, 2017
    Inventors: Harmeet Singh, Keith Gaff, Neil Benjamin, Keith Comendant
  • Patent number: 9696640
    Abstract: A lithographic apparatus including a first body including a heat source, a second body and a heater device is presented. The second body has a facing surface facing the first body via a gap between the first and second bodies. The heat source is for providing a heat flux to the second body via the gap. The heater device is attached to the facing surface. The heater device is configured to provide a further heat flux to the second body.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: July 4, 2017
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Adrianus Hendrik Koevoets, Theodorus Petrus Maria Cadee, Harmeet Singh
  • Patent number: 9659783
    Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 23, 2017
    Assignee: Lam Research Corporation
    Inventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh
  • Patent number: 9646861
    Abstract: A heating plate for use in a substrate support is configured to provide temperature profile control of a substrate supported on the substrate support in a vacuum chamber of a substrate processing apparatus. The heating plate includes an independently controllable heater zones operable to tune a temperature profile on an upper surface of the heating plate. The heater zones are each powered by two or more power lines wherein each power line is electrically connected to a different group of the heater zones and each respective heater zone is electrically connected to a different pair of power lines.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: May 9, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Harmeet Singh, Keith Gaff, Neil Benjamin, Keith Comendant
  • Patent number: 9645814
    Abstract: Technologies are disclosed for generating and publishing multi-platform application binaries from hosted websites or website source code. A developer can provide source code for a website or a link to a hosted website and identify target platforms for which application binaries should be created. The website is then modified for optimized presentation on devices on the specified target platforms. For example, page layouts, menu styles, image resolutions, and other aspects of the website can be modified for presentation on a mobile device, a tablet, a set top box, or other type of device. Source code is then generated for the target platforms that includes a web view component for rendering the website. A cross-platform compilation service then compiles the source code to generate native applications for the target platforms. The generated applications can then be provided to the developer or automatically submitted to application stores associated with the target platforms.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: May 9, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Miguel Azancot Roque, Arindam Bhattacharya, Mihir Kumar Choudhary, Samuel Jared Alston, Harmeet Singh Gorwara