Abstract: Systems and techniques for forming buffer gas microclimates around semiconductor wafers in environments external to a semiconductor processing chamber are disclosed. Such systems may include slot doors that may allow for single wafers to be removed from a multi-wafer stack while limiting outflow of buffer gas from a multi-wafer storage system, as well as buffer gas distributors that move in tandem with robot arms used to transport wafers for at least some of the movements of such robot arms.

Abstract: Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to prevent feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate.

Abstract: A replaceable upper chamber section of a plasma reaction chamber in which semiconductor substrates can be processed comprises a monolithic metal cylinder having a conical inner surface which is widest at a lower end thereof, an upper flange extending horizontally outward away from the conical inner surface and a lower flange extending horizontally away from the conical inner surface. The cylinder includes an upper annular vacuum sealing surface adapted to seal against a dielectric window of the plasma chamber and a lower annular vacuum sealing surface adapted to seal against a bottom section of the plasma chamber. A thermal mass at an upper portion of the cylinder is effective to provide azimuthal temperature uniformity of the conical inner surface. A thermal choke is located at a lower portion of the cylinder and is effective to minimize transfer of heat across the lower vacuum sealing surface.

Abstract: A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.

Abstract: Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to prevent feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate.

Abstract: A method for auto-correction of at least one malfunctioning thermal control element among an array of thermal control elements that are independently controllable and located in a temperature control plate of a substrate support assembly which supports a semiconductor substrate during processing thereof, the method including: detecting, by a control unit including a processor, that at least one thermal control element of the array of thermal control elements is malfunctioning; deactivating, by the control unit, the at least one malfunctioning thermal control element; and modifying, by the control unit, a power level of at least one functioning thermal control element in the temperature control plate to minimize impact of the malfunctioning thermal control element on the desired temperature output at the location of the at least one malfunctioning thermal control element.

Abstract: Systems and methods controlling ion energy within a plasma chamber are described. One of the systems includes an upper electrode coupled to a sinusoidal RF generator for receiving a sinusoidal signal and a nonsinusoidal RF generator for generating a nonsinusoidal signal. The system further includes a power amplifier coupled to the nonsinusoidal RF generator. The power amplifier is used for amplifying the nonsinusoidal signal to generate an amplified signal. The system includes a filter coupled to the power amplifier. The filter is used for filtering the amplified signal using a filtering signal to generate a filtered signal. The system includes a chuck coupled to the filter. The chuck faces at least a portion of the upper electrode and includes a lower electrode. The lower electrode is used for receiving the filtered signal to facilitate achieving ion energy at the chuck to be between a lower threshold and an upper threshold.

Abstract: A component of a plasma processing chamber having a protective liquid layer on a plasma exposed surface of the component The protective liquid layer can be replenished by supplying a liquid to a liquid channel and delivering the liquid through liquid feed passages in the component. The component can be an edge ring which surrounds a semiconductor substrate supported on a substrate support in a plasma processing apparatus wherein plasma is generated and used to process the semiconductor substrate. Alternatively, the protective liquid layer can be cured or cooled sufficiently to form a solid protective layer.

Abstract: A method is disclosed to form a patterned epitaxy template, on a substrate, to direct self-assembly of block copolymer for device lithography. A resist layer on a substrate is selectively exposed with actinic (e.g. UV or DUV) radiation by photolithography to provide exposed portions in a regular lattice pattern of touching or overlapping shapes arranged to leave unexposed resist portions between the shapes. Exposed or unexposed resist is removed with remaining resist portions providing the basis for a patterned epitaxy template for the orientation of the self-assemblable block copolymer as a hexagonal or square array. The method allows for simple, direct UV lithography to form patterned epitaxy templates with sub-resolution features.

Abstract: A method for protecting moderator access using a communication device. The method includes: displaying an interface for editing a conference call profile, the conference call profile including conference call scheduling information including one or more addressees for communicating with a conference call server, wherein the conference call scheduling information further includes a moderator access code and a participant access code; generating an indicator for the conference call profile for excluding sending of the moderator access code to invited participants; and storing the conference call profile including the indicator in a memory of the communication device. A communication device can be configured to perform the method.

Abstract: A method includes receiving a voltage and current measured at an output of an RF generator of a first plasma system and calculating a first model etch rate based on the voltage and current, and a power. The method further includes receiving a voltage and current measured at an output of the RF generator of a second plasma system, determining a second model etch rate based on the voltage and current at the output of the RF generator of the second plasma system, and comparing the second model etch rate with the first model etch rate. The method includes adjusting a power at the output of the RF generator of the second plasma system to achieve the first model etch rate associated with the first plasma system upon determining that the second model etch rate does not match the first model etch rate. The method is executed by a processor.

Abstract: A processing chamber having a chamber housing with a top and sidewalls is provided. The processing chamber has a seal for connecting the sidewalls of the chamber housing to a top of a lower chamber below the processing chamber. A substrate holder is attached to the sidewalls of the chamber housing. Further, a wafer lift ring supported by a side arm extending through the sidewalls has at least three posts each having at least one finger, the top of the fingers defining a first wafer handoff plane. The lower chamber has at least one lowest wafer support that defines a second wafer handoff plane where the height between the first wafer handoff plane and the second wafer handoff plane is not greater than a maximum vertical stroke of a transfer arm that is configured to transfer a wafer from the first wafer handoff plane and the second wafer handoff plane.

Abstract: A support for an object, e.g., a semiconductor substrate, includes a main body having a surface configured and arranged to have a plurality of projections. Each of the projections has an associated electrostatic actuator for displacing a free end of the associated projection relative to the main body at least in a direction in a plane parallel to a main surface of the object.

Abstract: A substrate support in a semiconductor plasma processing apparatus, comprises multiple independently controllable thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the thermal zones. A substrate support in which the substrate support is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the substrate support include bonding together ceramic or polymer sheets having thermal zones, power supply lines, power return lines and vias.

Abstract: Systems and methods controlling ion energy within a plasma chamber are described. One of the systems includes an upper electrode coupled to a sinusoidal RF generator for receiving a sinusoidal signal and a nonsinusoidal RF generator for generating a nonsinusoidal signal. The system further includes a power amplifier coupled to the nonsinusoidal RF generator. The power amplifier is used for amplifying the nonsinusoidal signal to generate an amplified signal. The system includes a filter coupled to the power amplifier. The filter is used for filtering the amplified signal using a filtering signal to generate a filtered signal. The system includes a chuck coupled to the filter. The chuck faces at least a portion of the upper electrode and includes a lower electrode. The lower electrode is used for receiving the filtered signal to facilitate achieving ion energy at the chuck to be between a lower threshold and an upper threshold.

Abstract: A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.

Abstract: A component of a plasma processing chamber having a protective liquid layer on a plasma exposed surface of the component. The protective liquid layer can be replenished by supplying a liquid to a liquid channel and delivering the liquid through liquid feed passages in the component. The component can be an edge ring which surrounds a semiconductor substrate supported on a substrate support in a plasma processing apparatus wherein plasma is generated and used to process the semiconductor substrate. Alternatively, the protective liquid layer can be cured or cooled sufficiently to form a solid protective layer.

Abstract: A synchronized pulsing arrangement for providing at least two synchronized pulsing RF signals to a plasma processing chamber of a plasma processing system is provided. The arrangement includes a first RF generator for providing a first RF signal. The first RF signal is provided to the plasma processing chamber to energize plasma therein, the first RF signal representing a pulsing RF signal. The arrangement also includes a second RF generator for providing a second RF signal to the plasma processing chamber. The second RF generator has a sensor subsystem for detecting values of at least one parameter associated with the plasma processing chamber that reflects whether the first RF signal is pulsed high or pulsed low and a pulse controlling subsystem for pulsing the second RF signal responsive to the detecting the values of at least one parameter.

Abstract: A lower electrode assembly for use in a plasma processing chamber comprises a metal base and upper and lower edge rings. The metal base comprises metal plates brazed together and forming a brazed line on a lower side surface of the base, an edge ring support surface extending horizontally inwardly from the lower side surface and an upper side surface above the edge ring support surface. The upper edge ring comprises a lower surface mounted on the edge ring support surface and the lower edge ring surrounds the lower side surface of the base with a gap between opposed surfaces of the upper and lower edge rings and between the lower edge ring and the outer periphery of the base. The gap has an aspect ratio of total gap length to average gap width sufficient to impede arcing at the location of the braze line.

Abstract: The disclosed embodiments relate to methods and apparatus for removing material from a substrate. In various implementations, conductive material is removed from a sidewall of a previously etched feature such as a trench, hole or pillar on a semiconductor substrate. In practicing the techniques herein, a substrate is provided in a reaction chamber that is divided into an upper plasma generation chamber and a lower processing chamber by a corrugated ion extractor plate with apertures therethrough. The extractor plate is corrugated such that the plasma sheath follows the shape of the extractor plate, such that ions enter the lower processing chamber at an angle relative to the substrate. As such, during processing, ions are able to penetrate into previously etched features and strike the substrate on the sidewalls of such features. Through this mechanism, the material on the sidewalls of the features may be removed.