Patents by Inventor Harold J. Hovel
Harold J. Hovel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8790804Abstract: A useful lifetime of an energy storage device can be extended by providing a series connection of a battery cell and an self-programming fuse. A plurality of series connections of a battery cell and an self-programming fuse can then be connected in a parallel connection to expand the energy storage capacity of the energy storage device. Each self-programming fuse can be a strip of a metal semiconductor alloy material, which electromigrates when a battery cell is electrically shorted and causes increases in the amount of electrical current therethrough. Thus, each self-programming fuse is a self-programming circuit that opens once the battery cell within the same series connection is shorted.Type: GrantFiled: January 12, 2012Date of Patent: July 29, 2014Assignee: International Business Machines CorporationInventors: Hariklia Deligianni, Harold J. Hovel, Fei Liu
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Patent number: 8723021Abstract: A solar cell includes a substrate having an N-region and a P-region, a first anti-reflective layer disposed on the substrate, a metallic contact disposed on the first anti-reflective layer, a second anti-reflective layer disposed on the first anti-reflective layer and the metallic contact, and a region partially defined by the first anti-reflective layer and the second anti-reflective layer having diffused metallic contact material operative to form a conductive path to the substrate through the first anti-reflective layer, the metallic contact, and the second anti-reflective layer.Type: GrantFiled: March 9, 2012Date of Patent: May 13, 2014Assignee: International Business Machines CorporationInventors: Harold J. Hovel, Rainer K. Krause, Zhengwen Li, Huilong Zhu
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Publication number: 20140109961Abstract: A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers.Type: ApplicationFiled: January 2, 2014Publication date: April 24, 2014Applicant: International Business Machines CorporationInventors: Stephen W. Bedell, Harold J. Hovel, Daniel A. Inns, Jee H. Kim, Alexander Reznicek, Devendra K. Sadana
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Publication number: 20140103286Abstract: The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and at least one memory cell coupled to the at least one photovoltaic cell. When the at least one photovoltaic cell is exposed to radiation, the at least one photovoltaic cell generates a current that causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and a reactive material coupled to the at least one photovoltaic cell, wherein a current from the at least one photovoltaic cell triggers an exothermic reaction in the reactive material.Type: ApplicationFiled: October 17, 2012Publication date: April 17, 2014Applicant: International Business Machines CorporationInventors: Jack O. Chu, Gregory M. Fritz, Harold J. Hovel, Young-Hee Kim, Dirk Pfeiffer, Kenneth P. Rodbell
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Patent number: 8665575Abstract: A photovoltaic module (10) with a plurality of solar cells (20) interconnected in serial and/or parallel arrangement within the module (10) is equipped with an overheat protection system (30) for suppressing damages of the photovoltaic module (10) due to defects of the solar cells (20). The overheat protection system (30) comprises a heat sensor (32) which is thermally coupled to a solar cell (20). The heat sensor (32) is physically integrated into an electrical switch (34, 36, 38) which is electrically connected to said solar cell (20).Type: GrantFiled: June 23, 2011Date of Patent: March 4, 2014Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Harold J. Hovel, Rainer Krause, Zhengwen Li, Kevin S. Petrarca, Gerd Pfeiffer, Kevin Prettyman, Carl J. Radens, Brian C. Sapp
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Patent number: 8653360Abstract: A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers.Type: GrantFiled: August 4, 2010Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Harold J. Hovel, Daniel A. Inns, Jee H. Kim, Alexander Reznicek, Devendra K. Sadana
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Publication number: 20140000693Abstract: A stack of a first anti-reflective coating (ARC) layer and a titanium layer is formed on a front surface of a semiconductor substrate including a p-n junction, and is subsequently patterned so that a semiconductor surface is physically exposed in metal contact regions of the front surface of the semiconductor substrate. The remaining portion of the titanium layer is converted into a titania layer by oxidation. A metal layer is plated on the metal contact regions, and a copper line is subsequently plated on the metal layer or a metal semiconductor alloy derived from the metal layer. A second ARC layer is deposited over the titania layer and the copper line, and is subsequently patterned to provide electrical contact to the copper line.Type: ApplicationFiled: February 28, 2013Publication date: January 2, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Satyavolu S. Papa Rao, Kathryn C. Fisher, Harold J. Hovel, Qiang Huang, Young-hee Kim, Susan Huang
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Publication number: 20140000691Abstract: A stack of a first anti-reflective coating (ARC) layer and a titanium layer is formed on a front surface of a semiconductor substrate including a p-n junction, and is subsequently patterned so that a semiconductor surface is physically exposed in metal contact regions of the front surface of the semiconductor substrate. The remaining portion of the titanium layer is converted into a titania layer by oxidation. A metal layer is plated on the metal contact regions, and a copper line is subsequently plated on the metal layer or a metal semiconductor alloy derived from the metal layer. A second ARC layer is deposited over the titania layer and the copper line, and is subsequently patterned to provide electrical contact to the copper line.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Applicant: International Business Machines CorporationInventors: Satyavolu S. PAPA RAO, Kathryn C. FISHER, Harold J. HOVEL, Qiang HUANG, Susan HUANG, Young-Hee KIM
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Patent number: 8614115Abstract: A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.Type: GrantFiled: October 29, 2010Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Harold J. Hovel, Rainer Klaus Krause, Kevin S. Petrarca, Gerd Pfeiffer, Kevin M. Prettyman, Carl Radens, Brian C. Sapp
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Patent number: 8569803Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: GrantFiled: August 13, 2012Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
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Publication number: 20130183553Abstract: A useful lifetime of an energy storage device can be extended by providing a series connection of a battery cell and an self-programming fuse. A plurality of series connections of a battery cell and an self-programming fuse can then be connected in a parallel connection to expand the energy storage capacity of the energy storage device. Each self-programming fuse can be a strip of a metal semiconductor alloy material, which electromigrates when a battery cell is electrically shorted and causes increases in the amount of electrical current therethrough. Thus, each self-programming fuse is a self-programming circuit that opens once the battery cell within the same series connection is shorted.Type: ApplicationFiled: January 12, 2012Publication date: July 18, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hariklia Deligianni, Harold J. Hovel, Fei Liu
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Patent number: 8486751Abstract: A method of manufacturing a photovoltaic cell using a semiconductor wafer having a front side and a rear side, wherein the photovoltaic cell produces electricity when the front side of the semiconductor wafer is illuminated.Type: GrantFiled: November 23, 2010Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Harold J. Hovel, Rainer Klaus Krause, Kevin S. Petrarca, Gerd Pfeiffer, Kevin M. Prettyman, Brian C. Sapp
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Patent number: 8441042Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: GrantFiled: September 17, 2009Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
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Patent number: 8426236Abstract: A grid stack structure of a solar cell, which includes a silicon substrate, wherein a front side of the silicon is doped with phosphorus to form a n-emitter and a back side of the silicon is screen printed with aluminum (Al) metallization; a dielectric layer, which acts as an antireflection coating (ARC), applied on the silicon; a mask layer applied on the front side to define a grid opening of the dielectric layer, wherein an etching method is applied to open an unmasked grid area; a light-induced plated nickel or cobalt layer applied to the front side with electrical contact to the back side Al metallization; a silicide layer formed by rapid thermal annealing of the plated nickel (Ni) or cobalt (Co); an optional barrier layer electrodeposited on the silicide; a copper (Cu) layer electrodeposited on the silicide/barrier film layer; and a thin protective layer is chemically applied or electrodeposited on top of the Cu layer.Type: GrantFiled: May 7, 2010Date of Patent: April 23, 2013Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Harold J. Hovel, Xiaoyan Shao
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Publication number: 20130056043Abstract: A solar energy conversion device comprises a vertical stack of at least two panels stacked in a hierarchy from an upper panel to a lower panel with each of the panels including a matching array of solar cells having a different energy bandgap from other panels of solar cells in the vertical stack of panels. Each panel in the vertical stack may be arranged with one of the panels having solar cells with a higher energy bandgap situated in the hierarchy and in the stack above others of the panels containing solar cells with a lower energy bandgap. The top surface of the device is adapted for receiving solar energy incident upon the uppermost panel. Each upper panel absorbs a fraction of sunlight with larger solar photon energies larger than the energy bandgap thereof.Type: ApplicationFiled: February 29, 2012Publication date: March 7, 2013Applicant: International Business Machines CorporationInventor: Harold J. Hovel
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Publication number: 20120305929Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: ApplicationFiled: August 13, 2012Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
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Publication number: 20120286236Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.Type: ApplicationFiled: July 23, 2012Publication date: November 15, 2012Applicant: International Business Machines CorporationInventors: Harold J. HOVEL, Qiang Huang, Xiaoyan Shao, James Vichiconti, George F. Walker
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Publication number: 20120285527Abstract: The instant disclosure relates to contact grids for use in photovoltaic cells, wherein a cross-section of the contact grid fingers is shaped as a trapezoid, as well as a method of making photovoltaic cells comprising these contact grids. The contact grids of the instant disclosure are cost effective and, due to their thick metal grids, exhibit minimum resistance. Despite having thick metal grids, the unique shape of the contact grid fingers of the instant disclosure allow the photovoltaic cells in which they are employed to retain more solar energy than traditional solar cells by reflecting incoming solar energy back onto the surface of the solar cell instead of reflecting this energy away from the cell.Type: ApplicationFiled: May 11, 2011Publication date: November 15, 2012Applicant: International Business Machines CorporationInventors: Ronald Goldblatt, Harold J. Hovel, Xiaoyan Shao, Steven E. Steen
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Patent number: 8294027Abstract: A method for fabricating a cell structure includes doping a substrate to form a N-region and a P-region, disposing a first anti-reflective layer on the substrate, disposing a metallic contact paste on the first anti-reflective layer, drying the metallic contact paste to form contacts, disposing a second anti-reflective layer on the first anti-reflective layer and the metallic contacts, and heating the cell structure, wherein heating the cell structure results in metallic contact material penetrating the first anti-reflective layer and contacting the substrate.Type: GrantFiled: January 19, 2010Date of Patent: October 23, 2012Assignee: International Business Machines CorporationInventors: Harold J. Hovel, Rainer K. Krause, Zhengwen Li, Huilong Zhu
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Patent number: 8273591Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.Type: GrantFiled: March 25, 2008Date of Patent: September 25, 2012Assignee: International Business Machines CorporationInventors: Harold J. Hovel, Qiang Huang, Xiaoyan Shao, James Vichiconti, George F. Walker