Abstract: A solar cell includes a substrate having an N-region and a P-region, a first anti-reflective layer disposed on the substrate, a metallic contact disposed on the first anti-reflective layer, a second anti-reflective layer disposed on the first anti-reflective layer and the metallic contact, and a region partially defined by the first anti-reflective layer and the second anti-reflective layer having diffused metallic contact material operative to form a conductive path to the substrate through the first anti-reflective layer, the metallic contact, and the second anti-reflective layer.

Abstract: A method for characterizing the electronic properties of a solar cell to be used in a photovoltaic module comprises the steps of performing a room temperature IV curve measurement of the solar cell and classifying the solar cell based on this IV curve measurement. In order to take stress-related effects into account, the solar cells are reclassified depending on the result of an additional measurement conducted on the solar cells under stress. This stress-related measurement may be gained from light induced thermography (LIT) yielding information on diode shunt areas within the solar cell.

Abstract: A multi-junction photovoltaic device includes a silicon substrate and a dielectric layer formed on the silicon substrate. A germanium layer is formed on the dielectric layer. The germanium includes a crystalline structure that is substantially similar to the crystalline structure of the silicon substrate. A first photovoltaic sub-cell includes a first plurality of doped semiconductor layers formed on the germanium layer. At least a second photovoltaic sub-cell includes a second plurality of doped semiconductor layers formed on the first photovoltaic sub-cell that is on the germanium layer that is on the dielectric layer.

Abstract: A solar energy conversion device comprises a vertical stack of at least two panels stacked in a hierarchy from an upper panel to a lower panel with each of the panels including a matching array of solar cells having a different energy bandgap from other panels of solar cells in the vertical stack of panels. Each panel in the vertical stack may be arranged with one of the panels having solar cells with a higher energy bandgap situated in the hierarchy and in the stack above others of the panels containing solar cells with a lower energy bandgap. The top surface of the device is adapted for receiving solar energy incident upon the uppermost panel. Each upper panel absorbs a fraction of sunlight with larger solar photon energies larger than the energy bandgap thereof and transmits solar photons with photon energies less than larger solar photon energies to a remaining one of the panels lower in the hierarchy and positioned lower in the stack.

Abstract: A multi-junction photovoltaic device includes a silicon substrate and a dielectric layer formed on the silicon substrate. A germanium layer is formed on the dielectric layer. The germanium includes a crystalline structure that is substantially similar to the crystalline structure of the silicon substrate. A first photovoltaic sub-cell includes a first plurality of doped semiconductor layers formed on the germanium layer. At least a second photovoltaic sub-cell includes a second plurality of doped semiconductor layers formed on the first photovoltaic sub-cell that is on the germanium layer that is on the dielectric layer.

Abstract: A photovoltaic device and method include a substrate layer having a plurality of structures including peaks and troughs formed therein. A continuous photovoltaic stack is conformally formed over the substrate layer and extends over the peaks and troughs. The photovoltaic stack has a thickness of less than one micron and is configured to transduce incident radiation into current flow.

Abstract: A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers.

Abstract: Two junction solar energy conversion devices, i.e. photovoltaic cells have a bottom silicon N+/P/P+ photovoltaic cell and an upper GaP N+/P/P+ photovoltaic cell containing quantum well layers which extend the wavelength range over which the GaP cell absorbs light. The quantum well layers are composed of materials other than Gallium Phosphide (GaP) and may be either pseudomorphic or metamorphic. Light trapping may be incorporated at the top surface of the GaP photovoltaic cell along with anti-reflective coatings, and light trapping may be incorporated on the bottom surface of the silicon cell. The bottom surface of the silicon photovoltaic cell is coated with a passivating dielectric layer and electrical contact to the silicon is made with conductive vias extending through the passivating layer.

Abstract: A photovoltaic module (10) with a plurality of solar cells (20) interconnected in serial and/or parallel arrangement within the module (10) is equipped with an overheat protection system (30) for suppressing damages of the photovoltaic module (10) due to defects of the solar cells (20). The overheat protection system (30) comprises a heat sensor (32) which is thermally coupled to a solar cell (20). The heat sensor (32) is physically integrated into an electrical switch (34, 36, 38) which is electrically connected to said solar cell (20).

Abstract: A method of forming patterned metallization by electrodeposition under illumination without external voltage supply on a photovoltaic structure or on n-type region of a transistor/junction.

Abstract: A grid stack structure of a solar cell, which includes a silicon substrate, wherein a front side of the silicon is doped with phosphorus to form a n-emitter and a back side of the silicon is screen printed with aluminum (Al) metallization; a dielectric layer, which acts as an antireflection coating (ARC), applied on the silicon; a mask layer applied on the front side to define a grid opening of the dielectric layer, wherein an etching method is applied to open an unmasked grid area; a light-induced plated nickel or cobalt layer applied to the front side with electrical contact to the back side Al metallization; a silicide layer formed by rapid thermal annealing of the plated nickel (Ni) or cobalt (Co); an optional barrier layer electrodeposited on the silicide; a copper (Cu) layer electrodeposited on the silicide/barrier film layer; and a thin protective layer is chemically applied or electrodeposited on top of the Cu layer.

Abstract: Processes for fabricating a contact grid for a photovoltaic cell generally includes providing a photovoltaic cell having an antireflective coating disposed on a sun facing side, the photovoltaic cell comprising a silicon substrate having a p-n junction; soft stamping a pattern of a UV sensitive photoresist and/or polymer onto the antireflective coating; exposing the UV sensitive photoresist and/or polymer to ultraviolet radiation to cure the UV sensitive photoresist and/or polymer; etching the pattern to form openings in the antireflective coating that define the contact grid; stripping the UV sensitive photoresist and/or polymer; and depositing a conductive metal into the openings defined by the pattern. The metal based paste can be aluminum based, which can be annealed at a relatively low temperature.

Abstract: A low cost method is described for forming a textured Si surface such as for a solar cell which includes forming a dielectric layer containing pinholes, anisotropically etching through the pinholes to form inverted pyramids in the Si surface and removing the dielectric layer thereby producing a high light trapping efficiency for incident radiation.

Abstract: A method for fabricating a cell structure includes doping a substrate to form a N-region and a P-region, disposing a first anti-reflective layer on the substrate, disposing a metallic contact paste on the first anti-reflective layer, drying the metallic contact paste to form contacts, disposing a second anti-reflective layer on the first anti-reflective layer and the metallic contacts, and heating the cell structure, wherein heating the cell structure results in metallic contact material penetrating the first anti-reflective layer and contacting the substrate.

Abstract: A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.

Abstract: A method of reducing the loss of elements of a photovoltaic thin film structure during an annealing process, includes depositing a thin film on a substrate, wherein the thin film includes a single chemical element or a chemical compound, coating the thin film with a protective layer to form a coated thin film structure, wherein the protective layer prevents part of the single chemical element or part of the chemical compound from escaping during an annealing process, and annealing the coated thin film structure to form a coated photovoltaic thin film structure, wherein the coated photovoltaic thin film retains the part of the single chemical element or the part of the chemical compound that is prevented from escaping during the annealing by the protective layer.

Abstract: A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.

Abstract: Processes for fabricating a contact grid for a photovoltaic cell generally includes providing a photovoltaic cell having an antireflective coating disposed on a sun facing side, the photovoltaic cell comprising a silicon substrate having a p-n junction; soft stamping a pattern of a UV sensitive photoresist and/or polymer onto the antireflective coating; exposing the UV sensitive photoresist and/or polymer to ultraviolet radiation to cure the UV sensitive photoresist and/or polymer; etching the pattern to form openings in the antireflective coating that define the contact grid; stripping the UV sensitive photoresist and/or polymer; and depositing a conductive metal into the openings defined by the pattern. The metal based paste can be aluminum based, which can be annealed at a relatively low temperature.

Abstract: A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.

Abstract: A lost cost method for fabricating SOI substrates is provided. The method includes forming a stack of p-type doped amorphous Si-containing layers on a semiconductor region of a substrate by utilizing an evaporation deposition process. A solid phase recrystallization step is then performed to convert the amorphous Si-containing layers within the stack into a stack of p-type doped single crystalline Si-containing layers. After recrystallization, the single crystalline Si-containing layers are subjected to anodization and at least an oxidation step to form an SOI substrate. Solar cells and/or other semiconductor devices can be formed on the upper surface of the inventive SOI substrate.