Patents by Inventor Harold J. Hovel
Harold J. Hovel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100218814Abstract: A method of reducing the loss of elements of a photovoltaic thin film structure during an annealing process, includes depositing a thin film on a substrate, wherein the thin film includes a single chemical element or a chemical compound, coating the thin film with a protective layer to form a coated thin film structure, wherein the protective layer prevents part of the single chemical element or part of the chemical compound from escaping during an annealing process, and annealing the coated thin film structure to form a coated photovoltaic thin film structure, wherein the coated photovoltaic thin film retains the part of the single chemical element or the part of the chemical compound that is prevented from escaping during the annealing by the protective layer.Type: ApplicationFiled: September 9, 2009Publication date: September 2, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hariklia Deligianni, Harold J. Hovel, Raman Vaidvanathan
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Publication number: 20100218813Abstract: A multi-junction photovoltaic device includes a silicon substrate and a dielectric layer formed on the silicon substrate. A germanium layer is formed on the dielectric layer. The germanium includes a crystalline structure that is substantially similar to the crystalline structure of the silicon substrate. A first photovoltaic sub-cell includes a first plurality of doped semiconductor layers formed on the germanium layer. At least a second photovoltaic sub-cell includes a second plurality of doped semiconductor layers formed on the first photovoltaic sub-cell that is on the germanium layer that is on the dielectric layer.Type: ApplicationFiled: July 31, 2009Publication date: September 2, 2010Applicant: International Business Machines CorporationInventors: SUPRATIK GUHA, Harold J. Hovel
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Publication number: 20100083997Abstract: Two junction solar energy conversion devices, i.e. photovoltaic cells have a bottom silicon N+/P/P+ photovoltaic cell and an upper GaP N+/P/P+ photovoltaic cell containing quantum well layers which extend the wavelength range over which the GaP cell absorbs light. The quantum well layers are composed of materials other than Gallium Phosphide (GaP) and may be either pseudomorphic or metamorphic. Light trapping may be incorporated at the top surface of the GaP photovoltaic cell along with anti-reflective coatings, and light trapping may be incorporated on the bottom surface of the silicon cell. The bottom surface of the silicon photovoltaic cell is coated with a passivating dielectric layer and electrical contact to the silicon is made with conductive vias extending through the passivating layer.Type: ApplicationFiled: October 2, 2008Publication date: April 8, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Harold J. Hovel
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Publication number: 20100083999Abstract: An energy conversion device comprises at least two thin film photovoltaic cells fabricated separately and joined by wafer bonding. The cells are arranged in a hierarchical stack of decreasing order of their energy bandgap from top to bottom. Each of the thin film cells has a thickness in the range from about 0.5 ?m to about 10 ?m. The photovoltaic cell stack is mounted upon a thick substrate composed of a material selected from silicon, glass, quartz, silica, alumina, ceramic, metal, graphite, and plastic. Each of the interfaces between the cells comprises a structure selected from a tunnel junction, a heterojunction, a transparent conducting oxide, and an alloying metal grid; and the top surface and/or the lower surface of the energy conversion device may contain light-trapping means.Type: ApplicationFiled: October 7, 2008Publication date: April 8, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Harold J. Hovel
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Publication number: 20100078056Abstract: A solar energy conversion device comprises a vertical stack of at least two panels stacked in a hierarchy from an upper panel to a lower panel with each of the panels including a matching array of solar cells having a different energy bandgap from other panels of solar cells in the vertical stack of panels. Each panel in the vertical stack may be arranged with one of the panels having solar cells with a higher energy bandgap situated in the hierarchy and in the stack above others of the panels containing solar cells with a lower energy bandgap. The top surface of the device is adapted for receiving solar energy incident upon the uppermost panel. Each upper panel absorbs a fraction of sunlight with larger solar photon energies larger than the energy bandgap thereof and transmits solar photons with photon energies less than larger solar photon energies to a remaining one of the panels lower in the hierarchy and positioned lower in the stack.Type: ApplicationFiled: October 1, 2008Publication date: April 1, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: HAROLD J. HOVEL
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Publication number: 20100075261Abstract: Processes for fabricating a contact grid for a photovoltaic cell generally includes providing a photovoltaic cell having an antireflective coating disposed on a sun facing side, the photovoltaic cell comprising a silicon substrate having a p-n junction; soft stamping a pattern of a UV sensitive photoresist and/or polymer onto the antireflective coating; exposing the UV sensitive photoresist and/or polymer to ultraviolet radiation to cure the UV sensitive photoresist and/or polymer; etching the pattern to form openings in the antireflective coating that define the contact grid; stripping the UV sensitive photoresist and/or polymer; and depositing a conductive metal into the openings defined by the pattern. The metal based paste can be aluminum based, which can be annealed at a relatively low temperature.Type: ApplicationFiled: September 22, 2008Publication date: March 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Harold J. Hovel, Rainer K. Krause, Kevin M. Prettyman
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Patent number: 7682846Abstract: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode.Type: GrantFiled: July 8, 2008Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Harold J. Hovel, Thermon E. McKoy
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Publication number: 20100037939Abstract: A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.Type: ApplicationFiled: August 12, 2008Publication date: February 18, 2010Inventors: Hans-Juergen Eickelmann, Michael Haag, Harold J. Hovel, Rainer Klaus Krause, Markus Schmidt, Xiaoyan Shao, Steven Erik Steen
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Publication number: 20100006850Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: ApplicationFiled: September 17, 2009Publication date: January 14, 2010Inventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
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Publication number: 20090242869Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.Type: ApplicationFiled: March 25, 2008Publication date: October 1, 2009Applicant: IBMInventors: Harold J. Hovel, Qiang Huang, Xiaoyan Shao, James Vichiconti, George F. Walker
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Publication number: 20090217967Abstract: Embodiments of the present invention provide a solar energy converter, which includes a silicon layer having at least two regions of a first and a second conductivity type that form a P-N junction, at least a portion of the silicon layer being porous, and pores in the portion of porous silicon containing a semiconductor material, the semiconductor material being different from silicon; and a first and a second electrode being placed at a bottom and a top surface of the silicon layer respectively. Methods of manufacturing the same are also provided.Type: ApplicationFiled: February 29, 2008Publication date: September 3, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold J. Hovel, Joel P. de Souza, Devendra K. Sadana
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Publication number: 20080283919Abstract: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode.Type: ApplicationFiled: July 8, 2008Publication date: November 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold J. Hovel, Thermon E. McKoy
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Patent number: 7288446Abstract: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes, In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode.Type: GrantFiled: September 6, 2005Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Harold J. Hovel, Thermon E. McKoy
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Patent number: 6955932Abstract: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode.Type: GrantFiled: October 29, 2003Date of Patent: October 18, 2005Assignee: International Business Machines CorporationInventors: Harold J. Hovel, Thermon E. McKoy
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Publication number: 20040266129Abstract: Disclosed herein is a method of providing improved electrical isolation in a separation by ion implanted oxide (SIMOX) process of making an SOI wafer. The method includes implanting ions into a substrate in a base dose implant conducted at a first energy level, implanting ions into the substrate at a second energy level in a second implant while the substrate is held at room temperature, and annealing the substrate to cause the implanted ions to be redistributed throughout the buried oxide (BOX) layer of the SOI wafer.Type: ApplicationFiled: June 27, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel P. DeSouza, Harold J. Hovel, Junedong Lee, Siegfried L. Maurer, Devendra K. Sadana, Dominic Schepis, Ghavam Shahidi, Neena Garg
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Publication number: 20030194846Abstract: A method of fabricating a high-quality silicon-on-insulator (SOI) substrate material having a buried oxide (BOX) region that has a thickness of about 300 nm or less is provided. The method employs multiple implant, multiple annealing steps to form the high-quality SOI substrate. In particular the inventive method includes at least a first oxygen ion implant where a primary oxide seed region is formed, a first annealing step, a second oxygen ion implant where a BOX-adjusting oxide seed region is formed and a second annealing step. The annealing steps convert the seed regions into buried oxide regions.Type: ApplicationFiled: April 11, 2002Publication date: October 16, 2003Applicant: International Business Machines Corp.Inventors: Harold J. Hovel, Maurice H. Norcott, Devendra K. Sadana
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Patent number: 6602757Abstract: A silicon-on-insulator substrate having improved thickness uniformity as well as a method of fabricating the same is provided. Specifically, improved thickness uniformity of a SOI substrate is obtained in the present invention by subjecting a bonded or SIMOX (separation by ion implantation of oxygen) SOI substrate to a high-temperature oxidation process that is capable of improving the thickness uniformity of said SOI substrate. During this high-temperature oxidation process surface oxidation of the superficial Si-containing (i.e., the Si-containing layer present atop the buried oxide (BOX) region) occurs; and (ii) internal thermal oxidation (ITOX), i.e., diffusion of oxygen via the superficial Si-containing layer into the interface that exists between the BOX and the superficial Si-containing layer also occurs.Type: GrantFiled: May 21, 2001Date of Patent: August 5, 2003Assignee: International Business Machines CorporationInventors: Harold J. Hovel, Devendra K. Sadana
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Patent number: 6548420Abstract: Procedures, analysis techniques, and correction methods are presented for assessing the electrical properties of the Si layer of silicon-on-insulator substrates. Detailed analysis and equations are outlined in a computer algorithm written in Mathcad for both the linear and saturated regions of FET behavior.Type: GrantFiled: March 21, 2002Date of Patent: April 15, 2003Assignee: International Business Machines CorporationInventor: Harold J. Hovel
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Publication number: 20020187619Abstract: A method for gettering metallic impurities located in a semiconductor substrate. In an exemplary embodiment of the invention, the method includes forming an insulating layer upon a donor wafer. A cleaving layer is ionically implanted, through the insulating layer, into the donor wafer. The cleaving layer is formed at a first depth with respect to the insulating layer. A gettering layer is also ionically implanted, through the insulating layer, into the donor wafer. The gettering layer is formed at a second depth with respect to said insulating layer, with second depth being less than the first depth. The donor wafer is then bonded, at the insulating layer, to a substrate wafer. The donor wafer is then fractured along the cleaving layer, and a section of the donor wafer is removed along the cleaving layer. Thereby, an active semiconductor device area is formed atop the gettering layer.Type: ApplicationFiled: May 4, 2001Publication date: December 12, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard L. Kleinhenz, Daniel Moy, Robert E. Bendernagel, Harold J. Hovel
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Publication number: 20020171106Abstract: A silicon-on-insulator substrate having improved thickness uniformity as well as a method of fabricating the same is provided. Specifically, improved thickness uniformity of a SOI substrate is obtained in the present invention by subjecting a bonded or SIMOX (separation by ion implantation of oxygen) SOI substrate to a high-temperature oxidation process that is capable of improving the thickness uniformity of said SOI substrate. During this high-temperature oxidation process surface oxidation of the superficial Si-containing (i.e., the Si-containing layer present atop the buried oxide (BOX) region) occurs; and (ii) internal thermal oxidation (ITOX), i.e., diffusion of oxygen via the superficial Si-containing layer into the interface that exists between the BOX and the superficial Si-containing layer also occurs.Type: ApplicationFiled: May 21, 2001Publication date: November 21, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold J. Hovel, Devendra K. Sadana