Abstract: A mechanism is provided for efficiently recycling a charge from a power domain that is discharging. A side of a discharging power domain normally coupled to a voltage supply is disconnected from the voltage supply. The side of the precharging power domain normally coupled to the voltage supply is currently disconnected from the voltage supply. The side of the discharging power domain normally coupled to the voltage supply is connected to a side of the precharging power domain normally coupled to the voltage supply. A side of the discharging power domain normally coupled to the ground is disconnected from ground. The side of the discharging power domain normally coupled to ground is connected to the voltage supply, thereby precharging the precharging power domain with the charge from the discharging power domain that would normally be lost due to leakage.

Abstract: Systems, methods and computer program product provide for pipelining out-of-order instructions. Embodiments comprise an instruction reservation station for short instructions of a short latency type and long instructions of a long latency type, an issue queue containing at least two short instructions of a short latency type, which are to be chained to match a latency of a long instruction of a long latency type, a register file, at least one execution pipeline for instructions of a short latency type and at least one execution pipeline for instructions of a long latency type; wherein results of the at least one execution pipeline for instructions of the short latency type are written to the register file, preserved in an auxiliary buffer, or forwarded to inputs of said execution pipelines. Data of the auxiliary buffer are written to the register file.

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A mechanism is provided for efficiently recycling a charge from a power domain that is discharging. A side of a discharging power domain normally coupled to a voltage supply is disconnected from the voltage supply. The side of the precharging power domain normally coupled to the voltage supply is currently disconnected from the voltage supply. The side of the discharging power domain normally coupled to the voltage supply is connected to a side of the precharging power domain normally coupled to the voltage supply. A side of the discharging power domain normally coupled to the ground is disconnected from ground. The side of the discharging power domain normally coupled to ground is connected to the voltage supply, thereby precharging the precharging power domain with the charge from the discharging power domain that would normally he lost due to leakage.

Abstract: A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A large block synthesis (LBS) process pre-optimizes selected submacros by synthesizing the submacros using timing assertions and placement abstracts, removing placement information, and assigning weights to the internal nets of the submacros that are much higher than weights used for external (e.g., top-level) nets. The timing assertions include an input arrival time, a required output arrival time, and an output pin capacitance loading for the logic block, and the placement abstract is generated by condensing input and output pins of the logic block at a center of gravity of the logic block. The submacros to be pre-optimized can automatically be identified using an attribute to indicate pre-optimization, or by determining that the submacro is one of many instances in the design. The higher weights for the submacro nets define soft-bounds for the logic which still allow relocation of submacro components. The pre-optimization results in significantly reduced synthesis runtime.

Abstract: A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decoder; an execution unit receiving and sending signals from and to the instruction scheduling unit; and a state machine. The method comprises: obtaining a number of instructions per cycle being issued to the instruction scheduling unit; determining, if the number of instruction per cycle being issued to the instruction scheduling unit is less than a threshold level, and then determining if at least two of the instructions being issued to the instruction scheduling unit are independent of each other only when the instructions per cycle is less than the threshold level; determining when at least two of the instructions being issued to the instruction scheduling unit are independent of each other; and power gating the microprocessor to gate off power to idle macros with a signal from the state machine.

Abstract: Multistage synthesis of hardware function operation descriptions is provided, which facilitates placement of logic cells in an integrated circuit design layout, and includes: parsing hardware function operation descriptions of a circuit to identify multiple instantiations of a type of logic function; performing, without shape restriction, a first synthesis on each logic function type identified as having multiple instantiations and producing an irregular-shaped logic unit layout for that logic function type; establishing an irregular-shaped blocking mask corresponding to a respective irregular-shaped logic unit layout produced by the first synthesis; creating a partial circuit layout by placing each irregular-shaped blocking mask multiple times corresponding to the multiple instantiations of the respective logic function type; and performing, employing the partial circuit layout, a second synthesis on the balance of the hardware function operation descriptions of the circuit outside the multiple instantiation

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decode unit; an execution unit coupled to receive and send signals from and to the instruction scheduling unit; and a state machine located within the execution unit, the method comprises: obtaining a number of instructions per cycle being issued to the instruction scheduling unit; determining, subsequent to obtaining the number of instructions per cycle, if the number of instruction per cycle being issued to the instruction scheduling unit is less than a threshold level, and then determining if at least two of the instructions being issued to the instruction scheduling unit are independent of each other only when the instructions per cycle is less than the threshold level; determining when at least two of the instructions being issued to the instruction scheduling unit are independent of each other; and power gating the microprocessor to gate off power to idle macros with a si

Abstract: An integrated circuitry structure includes at least first and second regions. An optical layer includes optical waveguides. A heat-conductive material transfers heat from at least the second region through the optical layer to a heat sink.

Abstract: An integrated circuit coupling device includes an integrated circuit package; and an optical data transmission medium connected to the integrated circuit package, and comprising a movable coolant, adapted to remove heat from the integrated circuit package, in operation.

Abstract: Multistage synthesis of hardware function operation descriptions is provided, which facilitates placement of logic cells in an integrated circuit design layout, and includes: parsing hardware function operation descriptions of a circuit to identify multiple instantiations of a type of logic function; performing, without shape restriction, a first synthesis on each logic function type identified as having multiple instantiations and producing an irregular-shaped logic unit layout for that logic function type; establishing an irregular-shaped blocking mask corresponding to a respective irregular-shaped logic unit layout produced by the first synthesis; creating a partial circuit layout by placing each irregular-shaped blocking mask multiple times corresponding to the multiple instantiations of the respective logic function type; and performing, employing the partial circuit layout, a second synthesis on the balance of the hardware function operation descriptions of the circuit outside the multiple instantiation

Abstract: An integrated circuit coupling device includes an integrated circuit package with N integrated circuit layers (L1-LN) arranged as a 3D stack; and a data transmission medium with n data transmission layers (l1-ln), wherein n?1 and N?2, and wherein the N integrated circuit layers are electrically connectable to the n data transmission layers.

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved.