Patents by Inventor Hau Thien Tran

Hau Thien Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7549105
    Abstract: Construction of Irregular LDPC (Low Density Parity Check) codes using RS (Reed-Solomon) codes or GRS (Generalized Reed-Solomon) codes. As described herein, a wide variety of irregular LDPC codes may be generated using GRS or RS codes. The corresponding LDPC matrix of such an irregular LDPC code may be constructed by performing partial-matrix processing (including decomposition and partial-matrix replacement thereof) of a parity check matrix that corresponds to a GRS-based regular LDPC code. Such an irregular LDPC code may be appropriately designed using these principles thereby generating a code that is suitable for use in wireless communication systems including those that comply with the recommendation practices and standards being developed by the IEEE (Institute of Electrical & Electronics Engineers) 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: June 16, 2009
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Kelly Brian Cameron, Tak K. Lee, Hau Thien Tran
  • Patent number: 7536629
    Abstract: Construction of LDPC (Low Density Parity Check) codes using GRS (Generalized Reed-Solomon) code. A novel approach is presented by which a GRS code may be employed to generate a wide variety of types of LDPC codes. Such GRS based LDPC codes may be employed within various types of transceiver devices implemented within communication systems. This approach may be employed to generate GRS based LDPC codes particular designed for various application arenas. As one example, such a GRS based LDPC code may be specifically designed for use in communication systems that operate in accordance with any standards and/or recommended practices of the IEEE P802.3an (10GBASE-T) Task Force.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: May 19, 2009
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Scott Richard Powell, Kelly Brian Cameron, Hau Thien Tran
  • Patent number: 7530002
    Abstract: Sub-matrix-based implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which an LDPC coded signal is decoded by processing 1 sub-matrix at a time. A low density parity check matrix corresponding to the LDPC code includes rows and columns of sub-matrices. For example, when performing bit node processing, 1 or more sub-matrices in a column are processed; when performing check node processing, 1 or more sub-matrices in a row are processed. If desired, when performing bit node processing, the sub-matrices in each column are successively processed together (e.g., all column 1 sub-matrices, all column 2 sub-matrices, etc.). Analogously, when performing check node processing, the sub-matrices in each row can be successively processed together (e.g., all row 1 sub-matrices, all row 2 sub-matrices in row 2, etc.).
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: May 5, 2009
    Assignee: Broadcom Corporation
    Inventors: Tak K. Lee, Hau Thien Tran, Ba-Zhong Shen, Kelly Brian Cameron
  • Patent number: 7515642
    Abstract: LDPC (Low Density Parity Check) coded 128 DSQ (Double Square QAM) constellation modulation and its associated labeling. A novel means is introduced by which a constellation may be arranged and mapping in its symbols may be determined to provide for improved performance. One application area in which this may be employed is transmission over twisted pair (typically copper) cabling existent within data centers of various networks. The operation of the IEEE 802.3 Ethernet local area networks currently being used (as well as those currently under development) would benefit greatly by employing the various principles presented herein. When this novel approach of an LDPC coded 128 DSQ constellation modulation combined with TH (Tomlinson-Harashima) preceding is employed within a communication device at a transmitter end of a communication channel (i.e., in a transmitter and/or a transceiver), the overall operation of a communication system may improve significantly when compared to prior techniques.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: April 7, 2009
    Assignee: Broadcom Corporation
    Inventors: Gottfried Ungerboeck, Ba-Zhong Shen, Scott Richard Powell, Kelly Brian Cameron, Hau Thien Tran
  • Patent number: 7516390
    Abstract: LDPC (Low Density Parity Check) coding and interleaving implemented in multiple-input-multiple-output (MIMO) communication systems. As described herein, a wide variety of irregular LDPC codes may be generated using GRS or RS codes. A variety of communication device types are also presented that may employ the error correcting coding (ECC) using a GRS-based irregular LDPC code, along with appropriately selected interleaving, to provide for communications using ECC. These communication devices may be implemented to in wireless communication systems including those that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: April 7, 2009
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Christopher J. Hansen, Joseph Paul Lauer, Kelly Brian Cameron, Tak K. Lee, Hau Thien Tran
  • Patent number: 7499503
    Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: March 3, 2009
    Assignee: Broadcom Corporation
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran, Christopher R. Jones, Thomas A. Hughes, Jr.
  • Patent number: 7500172
    Abstract: AMP (Accelerated Message Passing) decoder adapted for LDPC (Low Density Parity Check) codes. A novel approach is presented by which the LDPC coded signals may be decoded in a more efficient, faster, and less computationally intensive manner. Soft bit information, generated from decoding a higher layer square sub-matrix of a parity check matrix of the LDPC code, is employed to assist in the decoding of other square sub-matrices in subsequent layers. This approach allows the decoding of an LDPC code whose parity check matrix has column weight more than 1 (e.g., 2 or more), thereby allowing a much broader selection of LDPC codes to be employed in various communication systems. This approach also provides much improvement in terms of BER/BLER as a function of Eb/No (or SNR), and it can provide comparable (if not better) performance when performing significantly fewer (e.g., up to 50% fewer) decoding iterations that other approaches.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: March 3, 2009
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Hau Thien Tran, Kelly Brian Cameron
  • Patent number: 7472335
    Abstract: Symbol by symbol variable code rate capable communication device. A communication device is operable to perform processing of a variable code rate signal whose code rate varies on a symbol by symbol basis. This may involve performing encoding of input to generate the variable code rate signal; alternatively, this may involve performing decoding of a variable code rate signal. In doing so, this approach may involve using a single encoder and/or decoder (depending on the application). In some instances, a single device is operable to encode a first variable code rate signal (for transmission to another device) and to decode a second variable code rate signal (that has been received from another device). In addition, a method of coding (including one or both of encoding and decoding) may also operate of a variable code rate signal whose code rate varies on a symbol by symbol basis.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: December 30, 2008
    Assignee: Broadcom Corporation
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran
  • Patent number: 7464317
    Abstract: Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph. Decoding of LDPC coded signals is presented whereby edge messages may be updated using only multiplication (or log domain addition). By appropriate modification of the various calculations that need to be performed when updating edge messages, the calculations may be reduced to only performing product of terms functions. When implementing such functionality in hardware within a communication device that is operable to decode LDPC coded signals, this reduction in processing complexity greatly eases the actual hardware's complexity as well. A significant savings in processing resources, memory, memory management concerns, and other performance driving parameters may be made.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: December 9, 2008
    Assignee: Broadcom Corporation
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran
  • Patent number: 7460608
    Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: December 2, 2008
    Assignee: Broadcom Corporation
    Inventors: Kelly B. Cameron, Hau Thien Tran, Ba-Zhong Shen, Christopher R. Jones
  • Patent number: 7451386
    Abstract: LDPC (Low Density Parity Check) coded modulation hybrid decoding. A novel approach is presented wherein a combination of bit decoding and symbol level decoding (e.g., hybrid decoding) is performed for LDPC coded signals. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until a sufficient degree of precision is achieved. The symbol node updating of the bit edge messages involves using symbol metrics corresponding to the symbol being decoded as well as the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages involves using the bit edge messages most recently updated by symbol node updating. The symbol node updating also involves computing possible soft symbol estimates for the symbol during each decoding iteration.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: November 11, 2008
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Hau Thien Tran, Kelly Brian Cameron
  • Patent number: 7447985
    Abstract: Efficient design to implement min**/min**? or max**/max**? functions in LDPC (Low Density Parity Check) decoders. When compared to prior art approaches, the novel and efficient implementation presented herein allows for the use of substantially less hardware and surface area within an actual communication device implemented to perform these calculations. In certain embodiments, the min** processing (and/or max** processing) is implemented to assist in the computationally intensive calculations required to decoded LDPC coded signals. In one instance, this is operable to assist in check node processing when decoding LDPC coded signals. However, the efficient principles and architectures presented herein may be implemented within other communication device types to decode other types of coded signals as well.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: November 4, 2008
    Assignee: Broadcom Corporation
    Inventors: Hau Thien Tran, Kelly Brian Cameron, Ba-Zhong Shen
  • Patent number: 7447981
    Abstract: System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave. A novel approach is presented that combines different coding types within a communication system to perform various types of error correction. This combination of accommodating different coding types may be employed at either end of a communication channel (e.g., at a transmitter end when performing encoding and/or at a receiver end when performing decoding). By combining different coding types within a communication system, the error correcting capabilities of the overall system is significantly improved. The appropriate combination of turbo code and/or LDPC code along with RS code allows for error correction or various error types including random error and burst error (or impulse noise).
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: November 4, 2008
    Assignee: Broadcom Corporation
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran
  • Patent number: 7447984
    Abstract: System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave. A novel approach is presented that combines different coding types within a communication system to perform various types of error correction. This combination of accommodating different coding types may be employed at either end of a communication channel (e.g., at a transmitter end when performing encoding and/or at a receiver end when performing decoding). By combining different coding types within a communication system, the error correcting capabilities of the overall system is significantly improved. The appropriate combination of turbo code and/or LDPC code along with RS code allows for error correction or various error types including random error and burst error (or impulse noise).
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: November 4, 2008
    Assignee: Broadcom Corporation
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran
  • Patent number: 7440521
    Abstract: In a normalization process, overflow occurring in limited size registers, holding the alpha or beta values in a map decoder, may be overcome by subtracting a constant value from all of the alpha or beta values when they reach a limit. Because subtracting a constant value may slow down the computation, detection of a constant value may occur on one decoding cycle and normalization on the succeeding decoding cycle. A multiplexor type circuit can be used to direct either zeros, in the normalization case, or a most significant bit(s), in computations without normalization, into the register holding the alpha or beta values. To minimize the impact on the computation by the normalization process, the multiplexor circuit can be set by the previous decoder cycle so that the computation does not have to wait for the multiplexor to be set to normalization or normal computation.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: October 21, 2008
    Assignee: Broadcom Corporation
    Inventors: Hau Thien Tran, Kelly B. Cameron
  • Patent number: 7436902
    Abstract: Multi-dimensional space Gray code maps for multi-dimensional phase modulation as applied to LDPC (Low Density Parity Check) coded modulation. A novel approach is provided within LDPC coded modulation communication systems that employ multi-dimensional phase modulation, using m-D (multi-dimensional) Gray code maps, to provide for improved performance when compared to communication systems employing 1-D (single-dimensional) Gray code maps. This approach can generate all possible m-D Gray code maps for a 2m-D M PSK modulation system. For example, all of the 2-D Gray code maps may be generated for a communication system using 4-D 8 PSK modulation system (where m=2, and M=8). A variety decoding processing approaches may be employed to perform LDPC coded modulation decoding of multi-dimensional space Gray code mapped signals. The slightly increased decoding complexity (when compared to decoding 1-D Gray code mapped signals) is the computation of symbol metrics and their decomposition to bit metrics.
    Type: Grant
    Filed: June 12, 2004
    Date of Patent: October 14, 2008
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Tak K. Lee, Kelly Brian Cameron, Hau Thien Tran
  • Publication number: 20080215950
    Abstract: LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing. This novel approach to decoding of LDPC coded signals may be described as being LDPC bit-check parallel decoding. In some alternative embodiment, the approach to decoding LDPC coded signals may be modified to LDPC symbol-check parallel decoding or LDPC hybrid-check parallel decoding. A novel approach is presented by which the edge messages with respect to the bit nodes and the edge messages with respect to the check nodes may be updated simultaneously and in parallel to one another. Appropriately constructed executing orders direct the sequence of simultaneous operation of updating the edge messages at both nodes types (e.g., edge and check). For various types of LDPC coded signals, including parallel-block LDPC coded signals, this approach can perform decoding processing in almost half of the time as provided by previous decoding approaches.
    Type: Application
    Filed: August 29, 2007
    Publication date: September 4, 2008
    Applicant: BROADCOM CORPORATION
    Inventors: Ba-Zhong Shen, Hau Thien Tran, Kelly Brian Cameron
  • Patent number: 7421034
    Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Soloman encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: September 2, 2008
    Assignee: Broadcom Corporation
    Inventors: Kelly B. Cameron, Ba-Zhong Shen, Hau Thien Tran, Christopher R. Jones, Thomas Ashford Hughes, Jr.
  • Patent number: 7415079
    Abstract: Decoder design adaptable to decode coded signals using min* or max* processing. A very efficient means of min* processing or max* processing may be performed within a communication device to assist in the very complex and cumbersome calculations that are employed when decoding coded signals. The types of coded signals that may be decoded using min* processing or max* processing are varied, and they include LDPC (Low Density Parity Check) coded signals, turbo coded signals, and TTCM (Turbo Trellis Coded Modulation) coded signals, among other coded signal types. Many of the calculations and/or determinations performed within min* processing or max* processing are performed simultaneously and in parallel of one another thereby ensuring very fast operation. In a finite precision digital implementation, when certain calculated bits of min* or max* processing are available, they govern selection of resultants from among multiple calculations and determinations made simultaneously and in parallel.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: August 19, 2008
    Assignee: Broadcom Corporation
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran
  • Patent number: 7409628
    Abstract: Efficient design to implement LDPC decoder. The efficient design presented herein provides for a solution that is much easier, smaller, and has less complexity than other possible solutions. The use of a ping-pong memory structure (or pseudo-dual port memory structure) in conjunction with a metric generator near the decoder's front end allows parallel bit/check node processing. An intelligently operating barrel shifter operates with a message passing memory that is operable to store updated edges messages with respect to check nodes as well as updated edges messages with respect to bit nodes. Using an efficient addressing scheme allows the same memory structure to store the two types of edges messages with respect to bit nodes: (1) corresponding to information bits and (2) corresponding to parity bits. In addition, an intelligently designed hardware macro block may be instantiated a number of times into the decoder design to support ever greater design efficiency.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: August 5, 2008
    Assignee: Broadcom Corporation
    Inventors: Hau Thien Tran, Kelly Brian Cameron, Ba-Zhong Shen