Abstract: The present invention relates to a method for manipulating a tiny object, including: providing a charged particle beam; forming a non-uniform charge distribution in a fluid medium; and applying, to a tiny object, a gradient force formed by the non-uniform charge distribution. The present invention extends manipulation to a nanoscale, and can be applied to various microscopic tiny objects such as conductors, non-conductors, and living or non-living biological cells or organelles, and therefore surely promote great progress in the fields of physics, chemistry, biology and medicine.

Abstract: Methods for forming a nickel silicide material on a substrate are disclosed. The methods include depositing a first nickel silicide seed layer atop a substrate at a temperature of about 15° C. to about 27° C., annealing the first nickel silicide seed layer at a temperature of 400° C. or less such as over 350° C.; and depositing a second nickel silicide layer atop the first nickel silicide seed layer at a temperature of about 15° C. to about 27° C. to form the nickel silicide material.

Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.

Abstract: Methods and apparatus for forming a reverse selective etch stop layer are disclosed. Some embodiments of the disclosure provide interconnects with lower resistance than methods which utilize non-selective (e.g., blanket) etch stop layers. Some embodiments of the disclosure utilize reverse selective etch stop layers within a subtractive etch scheme. Some embodiments of the disclosure selectively deposit the etch stop layer by passivating the surface of the metal material.

Abstract: Current temperatures for an enclosure of a media handling device are monitored and managed using threshold temperature values. When a current temperature deviates below a threshold temperature value, commands are sent to modules of the device to start and idle their motors causing heat to be generated from current flowing to the motors. The heat radiates within the enclosure raising the current temperature. When the current temperature reaches a second threshold temperature value for the enclosure, second commands are sent to the modules of the device to stop idling their motors causing heat within the enclosure to dissipate and lowering the current temperature for the enclosure.

Abstract: A method for preparing an electrode material includes: a) producing a microspherical precursor by way of co-precipitation; b) forming an intermediate product by calcining the precursor with a stoichiometric amount of sodium carbonate, lithium carbonate and a structural stabilizer; and c) performing an ion exchange process to the intermediate product under molten LiNO3/LiCl to form a lumpy residue. An electrode for lithium-ion battery includes an electrode material having a general formula of Li[Li1/3(TMxAly)]O2, and lithium-ion battery comprising an electrode such as a cathode having the above electrode material are also addressed.

Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 ??·cm or less.

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

Abstract: Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.

Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.

Abstract: Methods and apparatus for processing a substrate are provided. For example, a method of processing a substrate comprises supplying oxygen (O2) into a processing volume of an etch chamber to react with a silicon-based hardmask layer atop a base layer of ruthenium to form a covering of an SiO-like material over the silicon-based hardmask layer and etching the base layer of ruthenium using at least one of O2 or chloride (Cl2) while supplying nitrogen (N2) to sputter some of the SiO-like material onto an exposed ruthenium sidewall created during etching.

Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.

Abstract: Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids.

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids.

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

Abstract: Embodiments of the disclosure provide methods which reduce or eliminate lateral growth of a selective tungsten layer. Further embodiments provide an integrated clean and deposition method which improves the selectivity of selectively deposited tungsten on trench structures. Additional embodiments provide methods for forming a more uniform and selective bottom-up gap fill for trench structures with improved film properties.

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.

Abstract: Methods and apparatus for processing a substrate are provided. For example, a method of processing a substrate comprises supplying oxygen (O2) into a processing volume of an etch chamber to react with a silicon-based hardmask layer atop a base layer of ruthenium to form a covering of an SiO-like material over the silicon-based hardmask layer and etching the base layer of ruthenium using at least one of O2 or chloride (Cl2) while supplying nitrogen (N2) to sputter some of the SiO-like material onto an exposed ruthenium sidewall created during etching.