Patents by Inventor He Ren

He Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250135445
    Abstract: The present application provides a main catalyst for preparing poly(4-methyl-1-pentene) and a use of the main catalyst. The main catalyst for preparing poly(4-methyl-1-pentene) of the present application has a structure represented by Formula I, in which R1 is selected from hydrogen or phenyl, and when R1 is selected from phenyl, R1 is fused with a naphthalene ring in the Formula I to form an anthracene ring; and R2 is selected from methyl or isopropyl. When the main catalyst of the present application is used in a catalytic system to catalyze homopolymerization of 4-methyl-1-pentene, the catalyst exhibits high catalytic activity, and the prepared poly(4-methyl-1-pentene) has high molecular weight, narrow molecular weight distribution and high isotacticity, and thus has broad market application prospects.
    Type: Application
    Filed: January 2, 2025
    Publication date: May 1, 2025
    Inventors: He REN, Yuru WANG, Yuxin GAO, Shuyan HE, Shuangyang NI, Guoxing YANG, Rui ZHANG, Xinglong ZHAO, Wei WU, Deshuai WEI
  • Publication number: 20240379420
    Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Shi YOU, He REN, Naomi YOSHIDA, Nikolaos BEKIARIS, Mehul NAIK, Martin Jay SEAMONS, Jingmei LIANG, Mei-Yee SHEK
  • Publication number: 20240363354
    Abstract: Semiconductor devices and methods for manufacturing the same are provided. The method includes epitaxially growing a doped crystalline silicon-containing layer over a source/drain feature and growing a doped amorphous silicon-containing layer over a field region of a semiconductor layer. The trench is formed in the semiconductor layer and the trench exposes the source/drain feature. The method further includes epitaxially growing an undoped crystalline silicon-containing capping layer over the doped crystalline silicon-containing layer and growing an undoped amorphous silicon-containing layer over the doped silicon-containing amorphous layer. The method further includes selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer relative to the silicon-containing crystalline capping layer. The method further includes removing the silicon-containing crystalline capping layer to expose the doped silicon-containing crystalline layer.
    Type: Application
    Filed: April 16, 2024
    Publication date: October 31, 2024
    Inventors: He REN, Raman GAIRE, Shi YOU, Pranav RAMESH, Houssam LAZKANI, Shawn THOMAS, Abhishek DUBE, Mehul B. NAIK, Songkram Sonny SRIVATHANAKUL
  • Publication number: 20240321641
    Abstract: A method includes forming a planarization layer to a position below an upper transistor device region of a base structure of an electronic device and above a lower transistor device region of the base structure. The base structure includes a plurality of features. The method further includes forming spacer material along the base structure and the planarization layer, modifying the spacer material formed along bottom trenches of the base structure to obtain modified spacer material, and forming a spacer layer by using a wet etch process to remove the modified spacer material. Modifying the spacer material formed along the bottom trenches of the base structure to obtain the modified spacer material includes performing a dry etch process targeting the spacer material formed along the bottom trenches of the base structure.
    Type: Application
    Filed: March 15, 2024
    Publication date: September 26, 2024
    Inventors: Hao Jiang, Jong Mun Kim, Jonathan Qian, He Ren, Mehul Naik
  • Patent number: 12066846
    Abstract: Current temperatures for an enclosure of a media handling device are monitored and managed using threshold temperature values. When a current temperature deviates below a threshold temperature value, commands are sent to modules of the device to start and idle their motors causing heat to be generated from current flowing to the motors. The heat radiates within the enclosure raising the current temperature. When the current temperature reaches a second threshold temperature value for the enclosure, second commands are sent to the modules of the device to stop idling their motors causing heat within the enclosure to dissipate and lowering the current temperature for the enclosure.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: August 20, 2024
    Assignee: NCR Atleos Corporation
    Inventors: Paul David Rutherford, Adam Delaney Boyd, Donald Iain MacInnes, He Ren
  • Patent number: 12062545
    Abstract: Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a tungsten-containing film that is substrate free of tungsten metal. The tungsten-containing film is then converted to a metallic tungsten film by exposure to a second process condition.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: August 13, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Ilanit Fisher, Chi-Chou Lin, Kedi Wu, Wen Ting Chen, Shih Chung Chen, Srinivas Gandikota, Mandyam Sriram, Chenfei Shen, Naomi Yoshida, He Ren
  • Patent number: 12046508
    Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: July 23, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shi You, He Ren, Naomi Yoshida, Nikolaos Bekiaris, Mehul Naik, Martin Jay Seamons, Jingmei Liang, Mei-Yee Shek
  • Publication number: 20240213088
    Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 ??·cm or less.
    Type: Application
    Filed: March 5, 2024
    Publication date: June 27, 2024
    Inventors: He REN, Hao JIANG, Shi YOU, Mehul B. NAIK
  • Patent number: 12002705
    Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: June 4, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: He Ren, Houssam Lazkani, Raman Gaire, Mehul Naik, Kuan-Ting Liu
  • Patent number: 11965236
    Abstract: Methods for forming a nickel silicide material on a substrate are disclosed. The methods include depositing a first nickel silicide seed layer atop a substrate at a temperature of about 15° C. to about 27° C., annealing the first nickel silicide seed layer at a temperature of 400° C. or less such as over 350° C.; and depositing a second nickel silicide layer atop the first nickel silicide seed layer at a temperature of about 15° C. to about 27° C. to form the nickel silicide material.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: April 23, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Minrui Yu, He Ren, Mehul Naik
  • Patent number: 11967527
    Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.
    Type: Grant
    Filed: June 18, 2022
    Date of Patent: April 23, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: He Ren, Hao Jiang, Mehul Naik
  • Patent number: 11955382
    Abstract: Methods and apparatus for forming a reverse selective etch stop layer are disclosed. Some embodiments of the disclosure provide interconnects with lower resistance than methods which utilize non-selective (e.g., blanket) etch stop layers. Some embodiments of the disclosure utilize reverse selective etch stop layers within a subtractive etch scheme. Some embodiments of the disclosure selectively deposit the etch stop layer by passivating the surface of the metal material.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: April 9, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Kevin Kashefi, Alexander Jansen, Mehul Naik, He Ren, Lu Chen, Feng Chen
  • Publication number: 20240111318
    Abstract: Current temperatures for an enclosure of a media handling device are monitored and managed using threshold temperature values. When a current temperature deviates below a threshold temperature value, commands are sent to modules of the device to start and idle their motors causing heat to be generated from current flowing to the motors. The heat radiates within the enclosure raising the current temperature. When the current temperature reaches a second threshold temperature value for the enclosure, second commands are sent to the modules of the device to stop idling their motors causing heat within the enclosure to dissipate and lowering the current temperature for the enclosure.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Paul David Rutherford, Adam Delaney Boyd, Donald Iain MacInnes, He Ren
  • Patent number: 11923244
    Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 ??·cm or less.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: March 5, 2024
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Hao Jiang, Shi You, Mehul B. Naik
  • Patent number: 11908696
    Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: February 20, 2024
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Hao Jiang, Mehul Naik, Wenting Hou, Jianxin Lei, Chen Gong, Yong Cao
  • Patent number: 11830725
    Abstract: Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: November 28, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Naomi Yoshida, He Ren, Hao Jiang, Chenfei Shen, Chi-Chou Lin, Hao Chen, Xuesong Lu, Mehul B. Naik
  • Patent number: 11776806
    Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: October 3, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xi Cen, Yakuan Yao, Yiming Lai, Kai Wu, Avgerinos V. Gelatos, David T. Or, Kevin Kashefi, Yu Lei, Lin Dong, He Ren, Yi Xu, Mehul Naik, Hao Chen, Mang-Mang Ling
  • Patent number: 11749532
    Abstract: Methods and apparatus for processing a substrate are provided. For example, a method of processing a substrate comprises supplying oxygen (O2) into a processing volume of an etch chamber to react with a silicon-based hardmask layer atop a base layer of ruthenium to form a covering of an SiO-like material over the silicon-based hardmask layer and etching the base layer of ruthenium using at least one of O2 or chloride (Cl2) while supplying nitrogen (N2) to sputter some of the SiO-like material onto an exposed ruthenium sidewall created during etching.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: September 5, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Hao Jiang, Chi Lu, He Ren, Mehul Naik
  • Publication number: 20230260825
    Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.
    Type: Application
    Filed: February 14, 2022
    Publication date: August 17, 2023
    Inventors: He REN, Houssam LAZKANI, Raman GAIRE, Mehul NAIK, Kuan-Ting LIU
  • Patent number: 11705366
    Abstract: Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: July 18, 2023
    Assignee: Micromaterials LLC
    Inventors: He Ren, Amrita B. Mullick, Regina Freed, Mehul Naik, Uday Mitra