Abstract: Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.

Abstract: Methods and apparatus for processing a substrate and etching a nickel silicide layer are provided herein. In some embodiments, a method of etching a nickel silicide film in a semiconductor device include: contacting a nickel silicide film disposed on a substrate in a process chamber with an etching gas sufficient to form one or more soluble or volatile products in order to reduce or eliminate re-deposition of products formed from the nickel silicide film upon the nickel silicide film.

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

Abstract: Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.

Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.

Abstract: Embodiments of the present disclosure provide methods and apparatus for forming and patterning features in a film stack disposed on a substrate. In one embodiment, a method for patterning a conductive layer on a substrate includes supplying a gas mixture comprising a chlorine containing gas at a first flow rate to etch a first conductive layer disposed on the substrate, lowing the chlorine containing gas in the first gas mixture to a second flow rate lower than the first flow rate to continue etching the first conductive layer, and increasing the chlorine containing gas in the first gas mixture to a third flow rate greater than the second flow rate to remove the first conductive layer from the substrate.

Abstract: Methods and apparatus for processing a substrate and etching a nickel silicide layer are provided herein. In some embodiments, a method of etching a nickel silicide film in a semiconductor device include: contacting a nickel silicide film disposed on a substrate in a process chamber with an etching gas sufficient to form one or more soluble or volatile products in order to reduce or eliminate re-deposition of products formed from the nickel silicide film upon the nickel silicide film.

Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.

Abstract: Techniques for generating a multidimensional forecast are provided. In one technique, multiple segments are generated, each comprising a different set of attribute values. For each segment, a set of prior content requests for the segment is determined based on historical data, a forecasted number of content requests is determined based on the set of prior content requests, and the forecasted number of content requests is stored in association with a set of attribute values corresponding to the segment. A request is received to forecast performance of a content delivery campaign based on a particular set of attribute values. In response to receiving the request, multiple segments that share the particular set of attribute values are identified. The forecasted number of content requests associated with each segment of the multiple segments are aggregated to generate aggregated performance data. A portion of the aggregated performance data is caused to be displayed.

Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

Abstract: Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.

Abstract: Methods for forming a nickel silicide material on a substrate are disclosed. The methods include depositing a first nickel silicide seed layer atop a substrate at a temperature of about 15° C. to about 27° C., annealing the first nickel silicide seed layer at a temperature of 400° C. or less such as over 350° C.; and depositing a second nickel silicide layer atop the first nickel silicide seed layer at a temperature of about 15° C. to about 27° C. to form the nickel silicide material.

Abstract: Methods and apparatus to form fully self-aligned vias are described. A first metal film is formed in the recessed first conductive lines and on the first insulating layer of a substrate comprising alternating conductive lines and a first insulating layer. Pillars and a sheet are formed from the first metal film. Some of the pillars and a portion of the sheet are selectively removed and a second insulating layer is deposited around the remaining pillars and sheet. The remaining pillars and sheet are removed to form vias and a trench in the second insulating layer. A third insulating layer is deposited in the vias and trench and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer.

Abstract: Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.

Abstract: Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure utilize a cap layer to protect an insulating layer in order to minimize bowing of the side walls during metal recess in a fully self-aligned via. The cap layer can be selectively removed, thus increasing the aspect ratio, by exposing the substrate to a hot phosphoric acid solution.

Abstract: Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.

Abstract: An integrated circuit is fabricated by chemical vapor deposition or atomic layer deposition of a metal film to metal film.

Abstract: Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.

Abstract: Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.

Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.