Abstract: Embodiments described herein provide a method for sealing a porous low-k dielectric film. The method includes forming a sealing layer on the porous low-k dielectric film using a cyclic process. The cyclic process includes repeating a sequence of depositing a sealing layer on the porous low-k dielectric film and treating the sealing layer until the sealing layer achieves a predetermined thickness. The treating of each intermediate sealing layer generates more reactive sites on the surface of each intermediate sealing layer, which improves the quality of the resulting sealing layer.

Abstract: Methods and apparatuses for forming a dual damascene structure utilizing a selective protection process to protect vias and/or trenches in the dual damascene structure while removing a hardmask layer from the dual damascene structure. In one embodiment, a method for removing a patterned hardmask layer from a substrate includes forming an organic polymer material on a dual damascene structure that exposes substantially a patterned hardmask layer disposed on an upper surface of the dual damascene structure, removing the patterned hardmask layer on the substrate, and removing the organic polymer material from the substrate.

Abstract: Embodiments described herein relate to methods for forming an air gap interconnect. A metal spacer layer is conformally deposited on a substrate having mandrel structures formed thereon. The metal spacer layer is etched to form spacer features and the mandrel structures are removed from the substrate. Various other dielectric deposition, patterning and etching steps may be performed to desirably pattern materials present on the substrate. Ultimately, a trench is formed between adjacent spacer features and a capping layer is deposited over the trench to form an air gap between the adjacent spacer features. For packaging purposes, an interconnect via may be configured to contact at least one of the spacer features adjacent the air gap.

Abstract: Embodiments of the present invention provide methods for forming an interconnection structure in semiconductor devices without breaking vacuum with minimum oxidation/atmosphere exposure. In one embodiment, a method for forming an interconnection structure for semiconductor devices includes supplying a barrier layer etching gas mixture into a first processing chamber having a substrate disposed therein to etch portions of a barrier layer exposed by a patterned metal layer until the underlying substrate is exposed, the first processing chamber disposed in a processing system, and forming a liner layer on the substrate covering the etched barrier layer in a second processing chamber disposed in the processing system.

Abstract: Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system.

Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer.

Abstract: Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.

Abstract: A method for forming an air gap structure in an integrated layer stack includes dry etching a mold layer disposed on the stack in a processing system under vacuum. The mold layer is disposed between one or more interconnects, and the process of dry etching of the mold layer exposes at least a portion of the interconnects. The method also includes depositing a liner layer over the exposed portion of the interconnects. In another embodiment, a method for forming an air gap structure in an integrated layer stack includes dry etching an oxide mold layer disposed on the stack in an a first processing chamber in a processing system under vacuum. The method also includes depositing a low-k material liner layer over the interconnects, wherein the liner has a thickness of less than about 2 nanometers. The methods disclosed herein are performed in a processing system without breaking vacuum.

Abstract: Methods of depositing thin, low dielectric constant layers that are effective diffusion barriers on metal interconnects of semiconductor circuits are described. A self-assembled monolayer (SAM) of molecules each having a head moiety and a tail moiety are deposited on the metal. The SAM molecules self-align, wherein the head moiety is formulated to selectively bond to the metal layer leaving the tail moiety disposed at a distal end of the molecule. A dielectric layer is subsequently deposited on the SAM, chemically bonding to the tail moiety of the SAM molecules.

Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

Abstract: A method of etching exposed patterned heterogeneous structures is described and includes a remote plasma etch formed from a reactive precursor. The plasma power is pulsed rather than left on continuously. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents selectively remove one material faster than another. The etch selectivity results from the pulsing of the plasma power to the remote plasma region, which has been found to suppress the number of ionically-charged species that reach the substrate. The etch selectivity may also result from the presence of an ion suppression element positioned between a portion of the remote plasma and the substrate processing region.

Abstract: An apparatus configured to remove metal etch byproducts from the surface of substrates and from the interior of a substrate processing chamber. A plasma is used in combination with a solid state light source, such as an LED, to desorb metal etch byproducts. The desorbed byproducts may then be removed from the chamber.

Abstract: A method of etching exposed patterned heterogeneous structures is described and includes a remote plasma etch formed from a reactive precursor. The plasma power is pulsed rather than left on continuously. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents selectively remove one material faster than another. The etch selectivity results from the pulsing of the plasma power to the remote plasma region, which has been found to suppress the number of ionically-charged species that reach the substrate. The etch selectivity may also result from the presence of an ion suppression element positioned between a portion of the remote plasma and the substrate processing region.

Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.

Abstract: In some embodiments, a plasma etching apparatus is provided for etching copper that includes (1) a chamber body having a process chamber adapted to receive a substrate; (2) an RF source coupled to an RF electrode; (3) a pedestal located in the processing chamber and adapted to support a substrate; and (4) a UV source configured to delivery UV light to the processing chamber during at least a portion of an etch process performed within the plasma etching apparatus. Numerous other aspects are provided.

Abstract: In one aspect, a plasma etching apparatus is disclosed. The plasma etching apparatus includes a chamber body having a process chamber adapted to receive a substrate, an RF source coupled to an RF electrode, a pedestal located in the processing chamber and adapted to support a substrate, a plurality of conductive pins adapted to contact and support the substrate during processing, and a DC bias source electrically coupled to the plurality of conductive pins. Etching methods are provided, as are numerous other aspects.

Abstract: A supercritical carbon dioxide-assisted solid-phase grafting modification method for polypropylene, comprises swelling polypropylene for 0.5 to 10 hours in supercritical carbon dioxide having dissolved vinyl monomer and an initiator, then slowly relieving the pressure; moving the polypropylene that has undergone the swelling process into a reaction kettle, and adding xylene as an interface agent, the mass of xylene being 1% of the polypropylene; increasing the temperature to between 65° C. and 165° C. under normal pressure, and reacting 1 to 10 hours to obtain modified polypropylene; the swelling permeation temperature during the swelling process is from 31° C. to 60° C., the swelling pressure is from 7.5 to 12 MPa; the initiator is an azo compound or a peroxide. In the present method, the grafting rate reaches 5.4%, the thermal property, polarity, and mechanical property all improve substantially, and hydrophilic property is substantially enhanced.

Abstract: A method of etching exposed patterned heterogeneous structures is described and includes a remote plasma etch formed from a reactive precursor. The plasma power is pulsed rather than left on continuously. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents selectively remove one material faster than another. The etch selectivity results from the pulsing of the plasma power to the remote plasma region, which has been found to suppress the number of ionically-charged species that reach the substrate. The etch selectivity may also result from the presence of an ion suppression element positioned between a portion of the remote plasma and the substrate processing region.

Abstract: Methods of removing residual polymer from vertical walls of a patterned dielectric layer are described. The methods involve the use of a gas phase etch to remove the residual polymer without substantially disturbing the patterned dielectric layer. The gas phase etch may be used on a patterned low-k dielectric layer and may maintain the low dielectric constant of the patterned dielectric layer. The gas phase etch may further avoid stressing the patterned low-k dielectric layer by avoiding the use of liquid etchants whose surface tension can upset delicate low-K features. The gas phase etch may further avoid the formation of solid etch by-products which cars also deform the delicate features.

Abstract: A network security active detecting system for connecting to at least one client end and a server end in a network system includes a networking-judging unit for judging whether a networking request of a client end is sent to an authorized network, a security condition detecting unit for determining the security level of the client end after the networking-judging unit confirms the networking request of the client end is sent to the authorized network, a configuration exchange unit for controlling the client and server ends to negotiate for a communication protocol identified during the networking so as to determine a security service routine, a Layer 3 packet process unit for processing packets transmitted between the client end and the server end with the security service routine according to the communication protocol, and a negotiating mechanism for confirming the networking between the client and server ends for releasing system resources.