Abstract: A cable conduit end for securing a cable to a cable abutment of a latch is provided. The cable conduit end having: a housing; an alignment feature incorporated into a surface of the housing; a flexible retention feature integrally formed with the conduit end, wherein the flexible retention feature is spring biased away from the housing to a first position; and a radial retention feature extending outwardly away from the housing, wherein the flexible retention feature is located proximate to a first end of the housing and the radial retention feature is located proximate to a second end of the housing.

Abstract: A cable return assist assembly for a vehicle latch mechanism, including: a housing; a cable; a guide feature secured to the cable; and a spring positioned about the cable, the spring contacting the housing at one end of the spring and the guide feature at an opposite end of the spring when the cable, the spring and the guide feature are installed into the housing, the housing having an opening that allows the spring and the guide feature to be inserted into a cavity of the housing and a portion of the cable is received in a first opening located at one end of the housing and another portion of the cable is received in a second opening located at an opposite end of the housing.

Abstract: The present invention describes a system for calibrating a plurality of cameras in an area. The system functions by using certain patterns with visible or invisible properties In addition, the system implements automatic re-calibration in a specific way to reduce human intervention, cost and time.

Abstract: The present invention describes a system for calibrating a plurality of cameras in an area. The system functions by using certain patterns with visible or invisible properties In addition, the system implements automatic re-calibration in a specific way to reduce human intervention, cost and time.

Abstract: The present invention describes a system for calibrating a plurality of cameras in an area. The system functions by using certain patterns with visible or invisible properties In addition, the system implements automatic re-calibration in a specific way to reduce human intervention, cost and time.

Abstract: A remote cinching actuator (40), which includes an integral motor (14) wherein its rotation will drive the two stage drive gears system (44, 46), that are coupled to a cable lever (42). This cable lever (42) is mechanically attached to a cinch lever (26) within the side door latch (10) by a cable. Said lever (26) will rotate on its pivot and move the cinch drive link (28). A bearing (54) attached to the cinch drive link (28) will move during the cinching operation, traveling through the canal of the cinch override lever (36), to maintain the traveling course of the cinch drive link and, thereby, allowing the interaction between said link and a claw (30) to rotate the latter to its closed/primary position.

Abstract: A cable conduit end for securing a cable to a cable abutment of a latch is provided. The cable conduit end having: a housing; an alignment feature incorporated into a surface of the housing; a flexible retention feature integrally formed with the conduit end, wherein the flexible retention feature is spring biased away from the housing to a first position; and a radial retention feature extending outwardly away from the housing, wherein the flexible retention feature is located proximate to a first end of the housing and the radial retention feature is located proximate to a second end of the housing.

Abstract: Disclosed is a control circuit for protecting MOSFETs in I/O buffers or other devices from overvoltage damage, especially during power ramp up. The control circuit can perform additional functions. In one embodiment an integrated circuit (IC) includes input/output (I/O) buffers coupled to an output supply voltage terminal that is configured to receive an output supply voltage Vddio. Each of the I/O buffers has a bias voltage generator that is configured to generate a first bias voltage with a magnitude that depends on a control signal; an output stage that receives the first bias voltage, wherein the output stage is configured to drive an I/O pad based upon a data signal received at the I/O buffer. The IC also includes an I/O buffer controller coupled to the I/O buffers and configured to generate the control signal based upon a magnitude of the output supply voltage Vddio.

Abstract: An integrated circuit (IC) includes an input/output (IO) circuit in a first power domain, coupled between a first and second power supply terminal, and an integrity monitor in a second power domain, coupled between a third and fourth power supply terminal. The IO circuit includes an external terminal configured to communicate signals external to the IC, and an internal circuit node configured to provide a tap signal, wherein the internal circuit node is neither the first power supply terminal nor the second power supply terminal. The integrity monitor has a counter configured to provide a count value by counting each time the tap signal reaches a threshold voltage, and is configured to provide an integrity fault indicator based at least in part on the count value, in which the integrity fault indicator indicates whether or not a signal provided or received by the external terminal is trustworthy.

Abstract: A multi-voltage, high voltage I/O buffer in low-voltage technology is disclosed. In one embodiment, the I/O buffer includes a logic circuit configured to generate a signal based on a data signal and a first control signal. A level shifter is coupled between a supply voltage terminal and a ground terminal, and the level shifter is generates first and second output signals in first and second voltage domains, respectively, at first and second nodes, respectively, based on the signal from the logic circuit. A control circuit is coupled between the second node and a third node. The control circuit transmits the second output signal to the third node when the first control signal is asserted, and the control circuit couples the third node to the ground terminal when the first control signal is not asserted.

Abstract: A multi-voltage, high voltage I/O buffer in low-voltage technology is disclosed. In one embodiment, the I/O buffer includes a logic circuit configured to generate a signal based on a data signal and a first control signal. A level shifter is coupled between a supply voltage terminal and a ground terminal, and the level shifter is generates first and second output signals in first and second voltage domains, respectively, at first and second nodes, respectively, based on the signal from the logic circuit. A control circuit is coupled between the second node and a third node. The control circuit transmits the second output signal to the third node when the first control signal is asserted, and the control circuit couples the third node to the ground terminal when the first control signal is not asserted.

Abstract: Disclosed is a control circuit for protecting MOSFETs in I/O buffers or other devices from overvoltage damage, especially during power ramp up. The control circuit can perform additional functions. In one embodiment an integrated circuit (IC) includes input/output (I/O) buffers coupled to an output supply voltage terminal that is configured to receive an output supply voltage Vddio. Each of the I/O buffers has a bias voltage generator that is configured to generate a first bias voltage with a magnitude that depends on a control signal; an output stage that receives the first bias voltage, wherein the output stage is configured to drive an I/O pad based upon a data signal received at the I/O buffer. The IC also includes an I/O buffer controller coupled to the I/O buffers and configured to generate the control signal based upon a magnitude of the output supply voltage Vddio.

Abstract: A circuit with a first transistor includes a first current electrode coupled to a first voltage supply, a second current electrode coupled to a first circuit node, and a gate electrode coupled to receive a first input signal. A second transistor includes a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a gate electrode coupled to receive a first bias voltage. A third transistor includes a first current electrode coupled to the second current electrode of the second transistor, a second current electrode coupled to a second circuit node, and a gate electrode. A fourth transistor includes a first current electrode coupled to the second circuit node, a second current electrode coupled to a third circuit node, and a gate electrode coupled to receive a second bias voltage. The gate electrode of the third transistor is coupled to the third circuit node.

Abstract: An embedded continuity test circuit is provided. An integrated circuit includes a bond pad and an oscillator circuit. The oscillator circuit is configured to generate an oscillator signal having a first frequency when the bond pad is coupled to a bond region of a package and a second frequency when the bond pad is not coupled to the bond region of the package.

Abstract: A latch having: a claw configured to rotate between an unlatched position and a latched position; a pawl configured for movement between an engaged position and a disengaged position, wherein the pawl retains the claw in the latched position when the pawl is in the engaged position and wherein the pawl releases the claw when it is in a disengaged position and the claw is free to move from the latched position to the unlatched position; a bumper located on the pawl to dampen noises as the pawl is moved by a portion of the claw; and wherein the detent lever is pivotally mounted to a frame of the latch proximate to a corner of an opening of the latch.

Abstract: A circuit includes a plurality of voltage supply terminals including a lowest voltage supply terminal, an N-type finFET, and a current path electrically coupled to the lowest voltage supply terminal, where the N-type finFET transistor is located in the current path. The N-type finFET transistor includes at least one semiconductor fin, a gate structure made of a gate material located over the at least one fin, an end structure of the gate material located over an end of the at least one fin, a source electrode, and a drain electrode. The at least one fin is located over a well region, and the end structure is electrically tied to the well region, in which the well region is not electrically tied to the lowest voltage supply terminal.

Abstract: A system for monitoring the degradation status of refueling hoses on air includes a device with at least one sensor adapted to produce data about the external surface of the refueling hose. The method for monitoring the degradation status of refueling hoses on air includes moving a device with at least one sensor along a refueling hose or moving a refueling hose with respect to the device, producing data about the external surface of the refueling hose from the at least one sensor, and analyzing the data for monitoring the degradation status of the refueling hose. It allows providing a system and method for monitoring the degradation status of refueling hoses on air that reduces the risk of personal injury associated to hose damage inspection and is cost saving.

Abstract: A receiver is provided. The receiver includes a first plurality of transistors configured and arranged as diodes connected in series and coupled between an input terminal and an output terminal. A first transistor of the first plurality is configured and arranged for receiving a signal at the input terminal having a voltage exceeding a voltage rating of the first transistor. A second plurality of transistors is configured and arranged as diodes connected in series and coupled between the output terminal and a voltage supply terminal. A second transistor includes a first current electrode coupled to a control electrode and a first current electrode of the first transistor and a control electrode coupled to a voltage source terminal. A third transistor includes a first current electrode coupled to a second current electrode of the second transistor at a first node.

Abstract: An embedded continuity test circuit is provided. An integrated circuit includes a bond pad and an oscillator circuit. The oscillator circuit is configured to generate an oscillator signal having a first frequency when the bond pad is coupled to a bond region of a package and a second frequency when the bond pad is not coupled to the bond region of the package.

Abstract: A receiver is provided. The receiver includes a first signal path and a second signal path coupled between an input terminal and an output terminal. A first transistor in the first signal path has a control electrode coupled to a voltage source terminal and a first current electrode coupled at the input terminal. The first transistor is configured and arranged for receiving a first signal at the first input terminal having a voltage exceeding a voltage rating of the first transistor. A second transistor in the first signal path has a first current electrode coupled to a second current electrode of the first transistor and a control electrode coupled to receive a first control signal. The second transistor is configured to form an open circuit in the first signal path when the first control signal is at a first state. A first resistor network in the second signal path is configured and arranged for attenuating the first signal.