Patents by Inventor Hector Sanchez
Hector Sanchez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8094769Abstract: A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit for generating phase-spread pulses based on a relationship between a first time attribute of the up signal or the down signal and a second time attribute of the phase-spread pulses. The PLL system further includes a voltage-controlled oscillator (VCO) for generating a VCO clock based on the phase-spread pulses. The PLL system may also include a charge pump that generates a pumping signal based on the phase-spread pulses.Type: GrantFiled: July 25, 2008Date of Patent: January 10, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Gayathri A. Bhagavatheeswaran, Lipeng Cao, Hector Sanchez
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Patent number: 8030983Abstract: A clock receiver (301) on an integrated circuit (202) includes a programmable AC voltage divider (502) for receiving, through an input capacitor (406), a clock signal (206) from a clock generator (204) off the integrated circuit and for outputting a modified signal that has a reduced voltage swing, an inverter (440) coupled to the programmable voltage divider, and a common mode setting circuit (506), coupled to an input and an output of the inverter. The common mode setting circuit sets and maintains a common mode at the input of the inverter in response to a voltage at the input of the inverter and a voltage at the output of the inverter. The strength of transistors in the common mode tracking circuit tracks the strength of transistors in the inverter such that the common mode at the input to the inverter tracks a trip point of the inverter.Type: GrantFiled: June 15, 2009Date of Patent: October 4, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Xinghai Tang, Hector Sanchez
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Patent number: 8018259Abstract: A method for a phase-locked loop (PLL) in an integrated circuit, wherein the PLL comprises a voltage-controlled oscillator (VCO). The method includes, in a training mode: (1) setting a control voltage of the VCO at a first voltage level; (2) increasing the control voltage of the VCO from the first voltage level to a second voltage level, until a loss of the feedback signal is detected; and (3) storing an indicator value corresponding to the second voltage level of the control voltage of the VCO. The method further includes, in a normal mode: (1) monitoring a voltage level of the control voltage of the VCO by generating a monitored indicator value corresponding to the voltage level of the control voltage of the VCO; and (2) asserting the loss of feedback signal based on a comparison of the monitored indicator value and the indicator value.Type: GrantFiled: January 28, 2010Date of Patent: September 13, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Hector Sanchez, Gayathri A. Bhagavatheeswaran, Xinghai Tang
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Publication number: 20110181326Abstract: A method for a phase-locked loop (PLL) in an integrated circuit, wherein the PLL comprises a voltage-controlled oscillator (VCO). The method includes, in a training mode: (1) setting a control voltage of the VCO at a first voltage level; (2) increasing the control voltage of the VCO from the first voltage level to a second voltage level, until a loss of the feedback signal is detected; and (3) storing an indicator value corresponding to the second voltage level of the control voltage of the VCO. The method further includes, in a normal mode: (1) monitoring a voltage level of the control voltage of the VCO by generating a monitored indicator value corresponding to the voltage level of the control voltage of the VCO; and (2) asserting the loss of feedback signal based on a comparison of the monitored indicator value and the indicator value.Type: ApplicationFiled: January 28, 2010Publication date: July 28, 2011Inventors: Hector Sanchez, Gayathri A. Bhagavatheeswaran, Xinghai Tang
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Publication number: 20110061927Abstract: A component for a vehicle latch assembly is provided, the component having: an electrical sub-system having a plurality of circuit paths each being electrically connected to a common ground, the electrical sub-system being molded into a pre-mold by a first molding process, the pre-mold comprising an encapsulation layer molded around the common ground and an at least one structural member secured to the encapsulation layer and at least one of the plurality of circuit paths, the structural member providing rigidity to the pre-mold; and a plurality of locating features extending from at least one of the encapsulation layer and the structural member.Type: ApplicationFiled: September 10, 2010Publication date: March 17, 2011Inventors: Mauro P. Bidinost, Hector Sanchez Rojas
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Patent number: 7898323Abstract: An amplifying circuit has an offset calibration mode and a normal mode. The amplifying circuit includes an amplifier having a non-inverting input and an inverting input for receiving, during the normal mode, a first input signal and a second input signal and an output for providing a high speed output signal, wherein the first input signal is a reference voltage or a high speed signal and the second input signal is a high speed signal. The amplifying circuit further includes a first transmission gate and a second transmission gate coupled in series between the non-inverting input and an inverting input that are enabled during the offset calibration mode. A benefit of this approach is that capacitance between the inverting and non-inverting inputs is reduced by the first and second transmission gates being in series. There is further benefit in reducing this capacitance by having each transmission gate receive an enable signal from a different source.Type: GrantFiled: June 5, 2009Date of Patent: March 1, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Joshua Siegel, Hector Sanchez
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Patent number: 7893741Abstract: Signal edge alignment embodiments include multiple delay stages connected in series. Each delay stage includes a delay line, an interface circuit, and a tap selection circuit. The delay line applies fixed-width delays to an input signal to produce delayed versions of the input signal at a plurality of taps. The interface circuit, which is characterized by an inherent interface circuit delay, passes one of the delayed versions to an interface circuit output in response to a control signal. The tap selection circuit determines a finally-identified tap of the plurality of taps by determining an initially-identified tap at which a delayed version of the input signal most closely has a desired alignment with the input signal, and by identifying the finally-identified tap in the control signal as a tap that occurs earlier in the delay line than the initially-identified tap. This compensates for the inherent delay of the delay stage.Type: GrantFiled: June 12, 2009Date of Patent: February 22, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Lipeng Cao, Khoi B. Mai, Hector Sanchez
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Patent number: 7880550Abstract: Apparatus are provided for a voltage-controlled oscillator module. A voltage-controlled oscillator module comprises an input node for receiving an input voltage, a voltage-controlled oscillator, and voltage translation circuitry coupled between the input node and the voltage-controlled oscillator. The voltage translation circuitry is configured to generate a control voltage based on the input voltage and the voltage-controlled oscillator generates an oscillating signal at an oscillation frequency in response to the control voltage. Biasing circuitry is coupled to the voltage translation circuitry, and the biasing circuitry is configured to adjust the ratio of the control voltage to the input voltage.Type: GrantFiled: June 12, 2009Date of Patent: February 1, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Khoi B. Mai, Hector Sanchez
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Patent number: 7872494Abstract: Components of a memory controller are calibrated in a select sequence to compensate for variances in skew and signal level variations. The offset bias of the receiver of the I/O cell and the termination resistance of the I/O cell are calibrated. The duty cycles of the transmit path and receive path associated with the I/O cell can be calibrated using the calibrated receiver. In one aspect, the driver of the I/O cell can be calibrated prior to calibrating the receiver. Performing the calibration processes of the memory controller in one of the particular sequences described herein improves the timing budgets for the signaling conducted by the memory controller.Type: GrantFiled: June 12, 2009Date of Patent: January 18, 2011Assignee: Freescale Semiconductor, Inc.Inventors: James A. Welker, Hector Sanchez, Joshua Siegel
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Patent number: 7863963Abstract: A circuit comprises first and second inverters, first, second, third, and fourth transistors, and an enabling circuit. The first and second inverters each have an input terminal for receiving one of the first or second input signals, an output terminal, and first and second supply terminals. The first transistor is coupled to a first power supply terminal, to the output terminal of the second inverter, and to the first inverter. The second transistor is coupled to the first power supply terminal, to the output terminal of the first inverter, and to the first supply terminal of the second inverter. The third and fourth transistor are coupled to the second supply terminals of the first and second inverters, respectively, and each includes a control electrode and a second current electrode. The enabling circuit is for controlling the third and fourth transistors to reduce a leakage current in the circuit.Type: GrantFiled: January 23, 2009Date of Patent: January 4, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Shayan Zhang, Andrew C. Russell, Hector Sanchez
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Publication number: 20100315141Abstract: Signal edge alignment embodiments include multiple delay stages connected in series. Each delay stage includes a delay line, an interface circuit, and a tap selection circuit. The delay line applies fixed-width delays to an input signal to produce delayed versions of the input signal at a plurality of taps. The interface circuit, which is characterized by an inherent interface circuit delay, passes one of the delayed versions to an interface circuit output in response to a control signal. The tap selection circuit determines a finally-identified tap of the plurality of taps by determining an initially-identified tap at which a delayed version of the input signal most closely has a desired alignment with the input signal, and by identifying the finally-identified tap in the control signal as a tap that occurs earlier in the delay line than the initially-identified tap. This compensates for the inherent delay of the delay stage.Type: ApplicationFiled: June 12, 2009Publication date: December 16, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Lipeng Cao, Khoi B. Mai, Hector Sanchez
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Publication number: 20100316167Abstract: A clock receiver (301) on an integrated circuit (202) includes a programmable AC voltage divider (502) for receiving, through an input capacitor (406), a clock signal (206) from a clock generator (204) off the integrated circuit and for outputting a modified signal that has a reduced voltage swing, an inverter (440) coupled to the programmable voltage divider, and a common mode setting circuit (506), coupled to an input and an output of the inverter. The common mode setting circuit sets and maintains a common mode at the input of the inverter in response to a voltage at the input of the inverter and a voltage at the output of the inverter. The strength of transistors in the common mode tracking circuit tracks the strength of transistors in the inverter such that the common mode at the input to the inverter tracks a trip point of the inverter.Type: ApplicationFiled: June 15, 2009Publication date: December 16, 2010Applicant: Freescale Semiconductor, Inc.Inventors: Xinghai TANG, Hector SANCHEZ
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Publication number: 20100315171Abstract: Apparatus are provided for a voltage-controlled oscillator module. A voltage-controlled oscillator module comprises an input node for receiving an input voltage, a voltage-controlled oscillator, and voltage translation circuitry coupled between the input node and the voltage-controlled oscillator. The voltage translation circuitry is configured to generate a control voltage based on the input voltage and the voltage-controlled oscillator generates an oscillating signal at an oscillation frequency in response to the control voltage. Biasing circuitry is coupled to the voltage translation circuitry, and the biasing circuitry is configured to adjust the ratio of the control voltage to the input voltage.Type: ApplicationFiled: June 12, 2009Publication date: December 16, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Khoi Mai, Hector Sanchez
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Publication number: 20100315119Abstract: Components of a memory controller are calibrated in a select sequence to compensate for variances in skew and signal level variations. The offset bias of the receiver of the I/O cell and the termination resistance of the I/O cell are calibrated. The duty cycles of the transmit path and receive path associated with the I/O cell can be calibrated using the calibrated receiver. In one aspect, the driver of the I/O cell can be calibrated prior to calibrating the receiver. Performing the calibration processes of the memory controller in one of the particular sequences described herein improves the timing budgets for the signaling conducted by the memory controller.Type: ApplicationFiled: June 12, 2009Publication date: December 16, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: James A. Welker, Hector Sanchez, Joshua Siegel
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Publication number: 20100310030Abstract: A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, in indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.Type: ApplicationFiled: June 8, 2009Publication date: December 9, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Gayathri A. Bhagavatheeswaran, Joseph P. Gergen, Arvind Raman, Hector Sanchez
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Publication number: 20100308912Abstract: An amplifying circuit has an offset calibration mode and a normal mode. The amplifying circuit includes an amplifier having a non-inverting input and an inverting input for receiving, during the normal mode, a first input signal and a second input signal and an output for providing a high speed output signal, wherein the first input signal is a reference voltage or a high speed signal and the second input signal is a high speed signal. The amplifying circuit further includes a first transmission gate and a second transmission gate coupled in series between the non-inverting input and an inverting input that are enabled during the offset calibration mode. A benefit of this approach is that capacitance between the inverting and non-inverting inputs is reduced by the first and second transmission gates being in series. There is further benefit in reducing this capacitance by having each transmission gate receive an enable signal from a different source.Type: ApplicationFiled: June 5, 2009Publication date: December 9, 2010Inventors: Joshua Siegel, Hector Sanchez
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Publication number: 20100308793Abstract: A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal of the phase locked loop. The phase detector provides a pulse having a width indicative of the phase difference. A phase measurement module determines a digital value based on the pulse width. Accordingly, the digital value provides an indication of the phase difference between the reference clock signal and the output clock signal. A series of the digital values can be recorded to indicate how the phase difference varies over time, thereby providing a useful characterization of device behavior.Type: ApplicationFiled: June 8, 2009Publication date: December 9, 2010Applicant: Freescale Semiconductor., Inc.Inventors: Gayathri A. Bhagavatheeswaran, Lipeng Cao, Hector Sanchez
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Patent number: 7838345Abstract: An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.Type: GrantFiled: May 2, 2006Date of Patent: November 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Zhonghai Shi, Bich-Yen Nguyen, Héctor Sánchez
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Patent number: 7816948Abstract: A voltage translator having an input which receives an input signal and an output which provides a level shifted output signal includes a first inverter having an input coupled to receive the input signal, a second inverter having an input coupled to an output of the first inverter, a third inverter having an input coupled to an output of the second inverter, a fourth inverter having an input coupled to receive the input signal and an output coupled to an output of the third inverter, a fifth inverter having an input coupled to an output of the fourth inverter and having an output coupled to the input of the third inverter, and a sixth inverter having an input coupled to the output of the fifth inverter and an output coupled to the output of the voltage translator. The second and fourth inverters are coupled to a calibration voltage supply terminal.Type: GrantFiled: June 9, 2009Date of Patent: October 19, 2010Assignee: Freescale Semiconductor, Inc.Inventor: Hector Sanchez
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Publication number: 20100207688Abstract: A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.Type: ApplicationFiled: November 19, 2009Publication date: August 19, 2010Inventors: RAVINDRARAJ RAMARAJU, DAVID R. BEARDEN, KENNETH R. BURCH, CHARLES E. SEABERG, HECTOR SANCHEZ, BRADLEY J. GARNI