Abstract: A circuit comprises first and second inverters, first, second, third, and fourth transistors, and an enabling circuit. The first and second inverters each have an input terminal for receiving one of the first or second input signals, an output terminal, and first and second supply terminals. The first transistor is coupled to a first power supply terminal, to the output terminal of the second inverter, and to the first inverter. The second transistor is coupled to the first power supply terminal, to the output terminal of the first inverter, and to the first supply terminal of the second inverter. The third and fourth transistor are coupled to the second supply terminals of the first and second inverters, respectively, and each includes a control electrode and a second current electrode. The enabling circuit is for controlling the third and fourth transistors to reduce a leakage current in the circuit.

Abstract: A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit for generating phase-spread pulses based on a relationship between a first time attribute of the up signal or the down signal and a second time attribute of the phase-spread pulses. The PLL system further includes a voltage-controlled oscillator (VCO) for generating a VCO clock based on the phase-spread pulses. The PLL system may also include a charge pump that generates a pumping signal based on the phase-spread pulses.

Abstract: An anti-gate leakage programmable capacitor including at least one capacitor having a first terminal coupled to a first node and a second terminal, a second node, and a control circuit which selectively couples the second terminal of the capacitor to the second node or which drives the second terminal to the same voltage as the first node. In one embodiment, the programmable capacitor includes multiple capacitors, an amplifier having an input coupled to the first node and an output, and a switch circuit coupled to the second node, to each second terminal of each capacitor and to the amplifier output. The switch circuit selectively switches each second terminal of each capacitor between the amplifier output and the second node. The switch circuit may include pairs of switches each controlled by a corresponding select signal to selectively switch a corresponding capacitor between the reference node and the output of the amplifier.

Abstract: An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.

Abstract: A voltage controlled oscillator (VCO) has a plurality of series-connected inverters. Within each inverter a first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series-connected inverters, and a second control electrode for receiving a first bias signal. A second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

Abstract: A level shifter circuit including first and second circuits and a protection layer. The first circuit receives an input signal and switches first and second nodes to opposite states within a first voltage range between first and second supply voltages. The second circuit switches the third and fourth nodes to opposite states within a second voltage range between third and fourth supply voltages in response to switching of the first and second nodes. The protection layer couples the first and second nodes to third and fourth nodes via respective first and second isolation paths. The isolation paths operate to keep the first and second nodes within the first voltage range and to keep the third and fourth nodes within the second voltage range. Isolation enables the use of thin gate-oxide devices for speed while extending the voltage range beyond the maximum voltage allowable for a single thin gate-oxide device.

Abstract: A VCO has a plurality of MIGFETs coupled to provide phase adjustment in response to receiving digital phase adjustment control signals. The VCO includes a ring oscillator implemented as a plurality of serially coupled inverters. A phase adjustment circuit is coupled to the output of each inverter. The phase adjustment circuit of each stage comprises a predetermined number of MIGFETs. In one embodiment, half of the MIGFETs are used to speed-up the phase/frequency of the OUTPUT signal a predetermined amount in response to receiving speed-up control signals. The other half of the MIGFETs are used to slow-down the phase/frequency of the OUTPUT signal a predetermined amount in response to the receiving slow-down control signals. The VCO requires relatively less surface area, is simple, and is easy to implement.

Abstract: An output driver circuit comprising a plurality of multiple gate field effect transistors (MGFETs) that provides an output signal is provided. Each output driver circuit may have a first MGFET gate for receiving a drive signal, a second MGFET gate for biasing purposes, and a current electrode for providing an output signal. Some embodiments provide a drive signal and a bias signal to the same MGFET device. Alternate embodiments provide the same drive signal (or alternately the same bias signal) to both gates of the same MGFET device. Some embodiments may provide an output driver circuit having variable output impedance. Predriver circuitry and/or bias control circuitry may optionally be used.

Abstract: A VCO has a plurality of MIGFETs coupled to provide phase adjustment in response to receiving digital phase adjustment control signals. The VCO includes a ring oscillator implemented as a plurality of serially coupled inverters. A phase adjustment circuit is coupled to the output of each inverter. The phase adjustment circuit of each stage comprises a predetermined number of MIGFETs. In one embodiment, half of the MIGFETs are used to speed-up the phase/frequency of the OUTPUT signal a predetermined amount in response to receiving speed-up control signals. The other half of the MIGFETs are used to slow-down the phase/frequency of the OUTPUT signal a predetermined amount in response to the receiving slow-down control signals. The VCO requires relatively less surface area, is simple, and is easy to implement.

Abstract: A voltage controlled oscillator (VCO) has a plurality of series-connected inverters. Within each inverter a first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series-connected inverters, and a second control electrode for receiving a first bias signal. A second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

Abstract: A high speed output buffer including an input circuit providing first and second signals within a first voltage range having a first common mode voltage, an AC interface receiving the first and second signals and providing first and second preliminary drive signals, a detection and correction circuit that corrects a state of the first preliminary drive signal AC coupled to the first signal, first and second drive circuits receiving the preliminary drive signals and providing first and second drive signals, where the first drive circuit operates within a second voltage range having a greater common mode voltage and where the second drive circuit operates within a third voltage range, and an output that switches an output node within a voltage range that is greater than a maximum voltage range. The first, second and third voltage ranges are each within the maximum voltage range suitable for thin-gate devices.

Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.

Abstract: A level shifter circuit including first and second circuits and a protection layer. The first circuit receives an input signal and switches first and second nodes to opposite states within a first voltage range between first and second supply voltages. The second circuit switches the third and fourth nodes to opposite states within a second voltage range between third and fourth supply voltages in response to switching of the first and second nodes. The protection layer couples the first and second nodes to third and fourth nodes via respective first and second isolation paths. The isolation paths operate to keep the first and second nodes within the first voltage range and to keep the third and fourth nodes within the second voltage range. Isolation enables the use of thin gate-oxide devices for speed while extending the voltage range beyond the maximum voltage allowable for a single thin gate-oxide device.

Abstract: A high speed output buffer including an input circuit providing first and second signals within a first voltage range having a first common mode voltage, an AC interface receiving the first and second signals and providing first and second preliminary drive signals, a detection and correction circuit that corrects a state of the first preliminary drive signal AC coupled to the first signal, first and second drive circuits receiving the preliminary drive signals and providing first and second drive signals, where the first drive circuit operates within a second voltage range having a greater common mode voltage and where the second drive circuit operates within a third voltage range, and an output that switches an output node within a voltage range that is greater than a maximum voltage range. The first, second and third voltage ranges are each within the maximum voltage range suitable for thin-gate devices.

Abstract: A programmable PLL including a receiver, a phase frequency detector, a charge pump, and a VCO. The receiver includes a programmable capacitor voltage divider that shifts voltage of an input clock to provide a level-shifted clock. The AC interface includes a state detection and correction circuit that ensures proper state of the level-shifted clock. The PLL includes a pulse delay modulator for generating delayed clock control signals. The VCO includes a programmable phase control circuit that dynamically adjusts phase using the delayed clock control signals. The VCO circuit includes a ring oscillator circuit with one or more phase control nodes. The programmable phase control circuit selectively couples devices to the phase control node using the clock control signals to adjust phase. The devices may be capacitors or transistors, each switched using switches controlled by the delayed clock control signals. The capacitors may be metal capacitors or semiconductor transistor capacitors.

Abstract: A copier apparatus includes a scanner for acquiring at least one image to be copied. Temporary storage is adapted to temporarily store the image only until the next subsequent print/copy job is scanned. At least one printing engine is used to print the image on a medium. In addition, a processor is preset to delete the image from the temporary storage after completion of printing of the image by the printing engine unless the user interface has previously received an instruction to reprint the image. If the user provides an instruction to reprint the image, the user interface is adapted to display a menu of reprint options. Then the image can be reprinted without having to be rescanned.

Abstract: A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.

Abstract: An anti-gate leakage programmable capacitor including at least one capacitor having a first terminal coupled to a first node and a second terminal, a second node, and a control circuit which selectively couples the second terminal of the capacitor to the second node or which drives the second terminal to the same voltage as the first node. In one embodiment, the programmable capacitor includes multiple capacitors, an amplifier having an input coupled to the first node and an output, and a switch circuit coupled to the second node, to each second terminal of each capacitor and to the amplifier output. The switch circuit selectively switches each second terminal of each capacitor between the amplifier output and the second node. The switch circuit may include pairs of switches each controlled by a corresponding select signal to selectively switch a corresponding capacitor between the reference node and the output of the amplifier.

Abstract: A programmable PLL including a receiver, a phase frequency detector, a charge pump, and a VCO. The receiver includes a programmable capacitor voltage divider that shifts voltage of an input clock to provide a level-shifted clock. The AC interface includes a state detection and correction circuit that ensures proper state of the level-shifted clock. The PLL includes a pulse delay modulator for generating delayed clock control signals. The VCO includes a programmable phase control circuit that dynamically adjusts phase using the delayed clock control signals. The VCO circuit includes a ring oscillator circuit with one or more phase control nodes. The programmable phase control circuit selectively couples devices to the phase control node using the clock control signals to adjust phase. The devices may be capacitors or transistors, each switched using switches controlled by the delayed clock control signals. The capacitors may be metal capacitors or semiconductor transistor capacitors.

Abstract: A back side body contact for a transistor that extends through an opening in an insulating layer located adjacent to the backside of the body. The backside contact is coupled to an interconnect on the backside. In some examples, the interconnect is coupled to an interconnect located with respect the other side of an active layer which is coupled to a body voltage bias source.