Abstract: A memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of string groups respectively connected to a corresponding select line, among a plurality of select lines. The peripheral circuit performs a program operation of data on the memory block. The control logic controls the program operation of the peripheral circuit. The memory block is connected to first to n-th word lines. The control logic is configured to control the peripheral circuit to perform a first program operation on a physical page, among physical pages that are included in a first string group, connected to an i-th word line, performs a second program operation on a physical page that is connected to an (i?1)-th word line, and perform a dummy program operation on a physical page that is connected to an (i+1)-th word line. Here, n is a natural number equal to or greater than 3, and i is a natural number greater than 0 and less than n?1.

Abstract: There are provided a memory device and an operating method thereof. The memory device includes: sub-blocks divided with respect to a buffer page in which buffer cells are included; a voltage generator for, in a program operation of a selected sub-block among the sub-blocks, applying a first pass voltage to unselected word lines connected to the selected sub-block, and applying a second pass voltage lower than the first pass voltage to unselected word lines connected to an unselected sub-block; and a buffer line circuit for selectively turning on or turning off the buffer cells by selectively applying a turn-on voltage or a turn-off voltage to buffer lines connected to the buffer cells. A position of the buffer page is set as a default according to a physical structure of memory cells included in the sub-blocks, and is reset according to an electrical characteristic of the memory cells.

Abstract: A semiconductor memory device includes a precharge block, a select block, a peripheral circuit, and control logic. The precharge block is connected to bit lines and includes memory cells in an erase state. The select block shares the bit lines with the precharge block and includes memory cells in a program state. The peripheral circuit performs erase operation on the select block. The control logic controls the peripheral circuit to turn on a first circuit connected to the precharge block and apply first voltage to global lines connected to the first circuit when erase voltage is applied to a source line commonly connected to the precharge block and the select block. The memory cells of the precharge block are turned on by the first voltage applied from the global lines, and the erase voltage applied to the source line is transferred to the bit lines through the precharge block.

Abstract: A semiconductor memory device includes a memory cell array, a page buffer, and control logic. The memory cell array includes a plurality of memory cells for storing data. The page buffer is coupled to at least one memory cell among the plurality of memory cells through a bit line and is configured to store data in the at least one memory cell. The control logic is configured to control an operation of the page buffer. The page buffer includes a first transistor coupled between the bit line and a first node, a second transistor coupled between the bit line and an external power voltage terminal, and an internal operation circuit coupled to the first node.

Abstract: A semiconductor memory device includes a memory string and a control logic. The memory string is connected between a common source line and a bit line and includes at least one first select transistor, a plurality of memory cells, and a plurality of second select transistors. The control logic is configured to apply a first voltage to a first group among second select lines respectively connected to the second select transistors, float a second group among the second select lines and then apply an erase voltage to the common source line, during an erase operation.

Abstract: A method of operating a semiconductor memory device includes performing a plurality of program loops for programming selected memory cells among a plurality of memory cells. Each of the plurality of program loops includes a program phase and a verify phase. The program phase includes setting a state of a select line connected to a selected memory block including the selected memory cells, wherein setting the state of the select line connected to the selected memory block comprises applying a voltage to the select line based on a program progress state of the selected memory cells, setting a state of a bit line connected to the selected memory block, applying a program voltage to a selected word line among word lines connected to the selected memory block and applying a pass voltage to an unselected word line.

Abstract: A semiconductor device is provided which includes: a first group including a plurality of first memory blocks; a second group including a plurality of second memory blocks; a first common source line connected to the first group; a second common source line connected to the second group; a source line voltage supplying circuit supplying a source line voltage; a first switch controlling a connection between the first common source line and the source line voltage supplying circuit; and a second switch controlling a connection between the second common source line and the source line voltage supplying circuit. When one first memory block among the plurality of first memory blocks of the first group is selected, the first switch may be turned on, and the second switch may be turned off.

Abstract: A method of operating a semiconductor device includes applying a first voltage to a first source select line coupled to first source select transistors of memory strings included in an unselected memory block, among memory blocks, floating the first source select line after the first voltage is applied thereto, applying a second voltage having a lower voltage level than the first voltage to a second source select line coupled to second source select transistors of the memory strings included in the unselected memory block, applying a precharge voltage to a common source line, and applying a program voltage to a word line coupled to selected memory cells of memory strings included in a selected memory block, among the memory blocks.

Abstract: An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

Abstract: A method of operating a semiconductor memory device includes a plurality of program loops for programming selected memory cells among a plurality of memory cells. Each of the plurality of program loops includes setting a state of a bit line connected to the selected memory cells, applying a program voltage to a word line connected to the selected memory cells, and performing a verify operation on the selected memory cells using a first pre-verify voltage, a second pre-verify voltage greater than the first pre-verify voltage, and a main verify voltage greater than the second pre-verify voltage. A first program permission cell, a second program permission cell, a third program permission cell, and a program prohibition cell are determined by performing the verify operation.

Abstract: A read operation on selected memory cells may be performed by a method of operating a semiconductor memory device. The method may include determining a read voltage to be used in the read operation among first to 2N?1-th read voltages, applying the determined read voltage to a selected word line connected to the selected memory cells, and applying a read pass voltage to unselected word lines based on whether the determined read voltage is a first read voltage. Here, N may be a natural number of 2 or more.

Abstract: Selected memory cells are programmed by a method of operating a semiconductor memory device. The method includes setting a state of bit lines connected to a selected memory block including the selected memory cells; applying a turn-on voltage to a drain select line connected to the selected memory block, and applying a turn-off voltage to a source select line connected to the memory block; starting to increase a voltage of word lines of a first group of word lines including unselected word lines which are not connected to the selected memory cells and a selected word line connected to the selected memory cells, among a plurality of word lines connected to the selected memory block; and starting to increase a voltage of word lines of a second group of word lines, not included in the first group of word lines, including unselected word lines connected to the selected memory block.

Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a read operation on the memory cells. The control logic controls the read operation of the peripheral circuit. During the read operation, the control logic controls the peripheral circuit so that a read voltage is applied to a selected word line among a plurality of word lines coupled to the memory cells, a first pass voltage is applied to an unselected word line disposed adjacent to the selected word line and a second pass voltage is applied to an unselected word line that is not disposed adjacent thereto. The peripheral circuit adjusts a magnitude of the first or second pass voltage based on a temperature of the semiconductor memory device.

Abstract: A semiconductor memory device includes a cell string and a peripheral circuit. The cell string includes at least one drain select transistor that is connected to a bit line, at least one source select transistor that is connected to a common source line, and a plurality of memory cells that are connected between the drain select transistor and the source select transistor. The peripheral circuit performs a read operation on a selected memory cell among the plurality of memory cells. The peripheral circuit is configured to read data that is stored in the selected memory cell by applying a read voltage to a selected word line among word lines that are connected to the plurality of memory cells and by applying a pass voltage to unselected word lines, and configured to transmit a boosting prevention voltage to a channel region in the cell string while applying an equalizing voltage to the word lines.

Abstract: A semiconductor memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes a plurality of string groups respectively connected to a corresponding source select line among a plurality of source select lines. The peripheral circuit is configured to perform a program operation of storing data within the memory block. The control logic controls the program operation of the peripheral circuit. The plurality of source select lines are grouped into a plurality of source select line groups. The control logic controls the peripheral circuit to increase a voltage of a first source select line group including a source select line connected to a selected string group to a first level among the plurality of source select line groups.

Abstract: A semiconductor memory device, and a method of operating the same, includes a memory cell array and a peripheral circuit. The memory cell array includes memory cells, each storing N bits of data. The peripheral circuit performs a program operation on a physical page including selected memory cells. The peripheral circuit is configured to receive pieces of data of N logical pages and program the pieces of data of the N logical pages to the physical page based on a logic code. The logic code is determined to equalize numbers of sensing operations required to read the pieces of data of the N logical pages. Weak read levels are assigned, using the logic code, to read data of a logical page for which the number of sensing operations is smallest.

Abstract: A semiconductor memory device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory blocks coupled to a common source line. The peripheral circuit performs a program operation on a memory block selected from among the memory blocks. The control logic controls the program operation of the peripheral circuit. The memory blocks are coupled to corresponding source select lines, io respectively, The program operation includes a plurality of program loops, each including a channel precharge operation. During the channel precharge operation, the control logic controls the peripheral circuit so that the common source line floats and a voltage of a source select line coupled to an unselected memory block, among the memory blocks, is increased.

Abstract: A semiconductor memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes dummy memory cells connected to dummy word lines and normal memory cells connected to normal word lines. The peripheral circuit performs an erase operation on the memory block. The control logic controls an operation of the peripheral circuit. The control logic controls the peripheral circuit to perform a pre-program operation on first dummy memory cells connected to first dummy word lines among the dummy word lines, in response to an erase command for the memory block, and perform a pre-program operation on second dummy memory cells connected to second dummy word lines among the dummy word lines, after the pre-program operation on the first dummy memory cells. The control logic controls the peripheral circuit to perform an erase operation on the normal memory cells.

Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.

Abstract: A semiconductor memory device, and a method of operating the same, includes a memory cell array and a peripheral circuit. The memory cell array includes memory cells, each storing N bits of data. The peripheral circuit performs a program operation on a physical page including selected memory cells. The peripheral circuit is configured to receive pieces of data of N logical pages and program the pieces of data of the N logical pages to the physical page based on a logic code. The logic code is determined to equalize numbers of sensing operations required to read the pieces of data of the N logical pages. Weak read levels are assigned, using the logic code, to read data of a logical page for which the number of sensing operations is smallest.