Patents by Inventor Hee Youl An

Hee Youl An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and operating method of the semiconductor device
    Patent number: 10790024
    Abstract: A semiconductor device and method of operating a semiconductor device, the semiconductor device includes memory strings coupled between a common source line and a bit line, and a peripheral circuit coupled to the memory strings through a plurality of word lines and a dummy word line, and configured to set bias of the word lines and the dummy word line before performing a read operation, wherein the peripheral circuit applies a first pass voltage to the word lines concurrently with applying an initial voltage lower than the first pass voltage to the dummy word line, and increases the first pass voltage and the initial voltage to a second pass voltage to set the bias of the word lines and the dummy word line.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Han Soo Joo, Ji Hyun Seo, Hee Youl Lee
  • Semiconductor memory device and operating method thereof
    Patent number: 10790006
    Abstract: The semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation for the plurality of memory cells in the memory cell array. The control logic controls the peripheral circuit and the memory cell array such that, during the program operation for the plurality of memory cells, pre-bias voltages are applied to a plurality of word lines coupled to the plurality of memory cells to precharge channel regions of the plurality of memory cells. Furthermore, different pre-bias voltages are applied to the plurality of word lines depending on the relative positions of the word lines.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Operating method of memory device using channel boosting before read or verify operation
    Patent number: 10790033
    Abstract: Provided herein are a memory device and an operating method thereof. The memory device may include a plurality of memory blocks and one or more peripheral circuits. Each of the plurality of memory blocks may include a plurality of cell strings. The one or more peripheral circuits may perform one or more operations on the plurality of memory blocks. The operations may include turning off select transistors of the cell strings included in the memory blocks, increasing channel voltages of the cell strings included in the memory blocks, turning on, among select transistors included in the memory blocks, select transistors included in a selected memory block, and performing a read or a verify operation on the selected memory block.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • SEMICONDUCTOR DEVICE AND METHOD OF OPERATING SEMICONDUCTOR DEVICE
    Publication number: 20200258585
    Abstract: Provided herein may be a semiconductor device and a method of operating a semiconductor device. The method may include: performing a first program operation on a selected memory cell using a first program pulse, a first bit line voltage, a first pre-verify voltage, and a first main verify voltage, with a first level difference between the first pre-verify voltage and the first main verify voltage; and performing a second program operation on the selected memory cell using a second program pulse, a second bit line voltage, a second pre-verify voltage, and a second main verify voltage, with a second level difference between the second pre-verify voltage and the second main verify voltage. The second level difference may be less than the first level difference, and the second bit line voltage may have a level higher than a level of the first bit line voltage.
    Type: Application
    Filed: October 4, 2019
    Publication date: August 13, 2020
    Inventors: Hee Youl LEE, Ji Hyun SEO, Se Hoon KIM
  • Memory device and method of operating the same
    Patent number: 10720212
    Abstract: A memory device with a plurality of memory block may include a plurality of memory cells constituting a memory blocks, and two or more select transistors coupled to the plurality of memory cells constituting the memory block and configured to select the memory block, the two or more select transistors having different threshold voltages from one another.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: July 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Memory device and operating method thereof
    Patent number: 10699767
    Abstract: A memory device includes a memory block coupled to a plurality of word lines arranged in parallel with each other between a first select line and a second select line. Further included are peripheral circuits supplying a verify voltage and a pass voltage to the first select line, the second select line, and the word lines, selectively discharging the first select line, the second select line and the word lines, and verifying memory cells coupled to a selected word line of the word lines. Also, included is a control logic controlling the peripheral circuits so that potentials of the selected word line, unselected word lines and the first and second select lines are the same as each other after verifying the memory cells and the first and second select lines are discharged after discharging the selected and unselected word lines, and an operating method thereof.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF
    Publication number: 20200202933
    Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.
    Type: Application
    Filed: July 3, 2019
    Publication date: June 25, 2020
    Inventors: Han Soo JOO, Bong Yeol PARK, Ji Hyun SEO, Hee Youl LEE
  • SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
    Publication number: 20200185047
    Abstract: A method of operating a semiconductor memory device includes dummy-programming selected memory cells representing all the memory cells to be programmed for a programming operation. The method also includes determining as a first group of memory cells those selected memory cells having threshold voltages less than or equal to a reference threshold voltage and determining as a second group of memory cells those selected memory cells having threshold voltages greater than the reference threshold voltage. The method further includes programming the selected memory cells by applying a first bit line voltage to the memory cells of the first group, applying a second bit line voltage different from the first bit line voltage to the memory cells of the second group, and applying a same program pulse to the memory cells of the first and second groups.
    Type: Application
    Filed: October 10, 2019
    Publication date: June 11, 2020
    Applicant: SK hynix Inc.
    Inventor: Hee Youl LEE
  • MEMORY SYSTEM AND OPERATING METHOD THEREOF
    Publication number: 20200183776
    Abstract: Disclosed is a memory system and a method of operating the memory system. The memory system includes a semiconductor memory device configured to read data stored in a selected logical page among a plurality of logical pages by applying different read voltages to a selected word line corresponding to the plurality of logical pages. The memory system also includes a controller configured to perform an operation for detecting and correcting an error of the data whenever each of the read voltages is applied to the selected word line.
    Type: Application
    Filed: July 11, 2019
    Publication date: June 11, 2020
    Applicant: SK hynix Inc.
    Inventors: Hee Youl LEE, Dong Kyu KIM
  • Memory device and operating method thereof
    Patent number: 10672480
    Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventors: Hee Youl Lee, Kyoung Cheol Kwon, Dong Hun Lee, Min Kyu Jeong, Sung Yong Chung
  • SEMICONDUCTOR DEVICE AND OPERATING METHOD OF THE SEMICONDUCTOR DEVICE
    Publication number: 20200168280
    Abstract: A semiconductor device includes strings each having a plurality of memory cells. The strings are coupled between a common source line and a bit line. A method of operating the semiconductor device includes applying a pre-program voltage to a selected word line coupled to a selected memory cell and to an unselected word line coupled to an unselected memory cell adjacent to the selected memory cell among the plurality of memory cells. The method further includes applying a first program voltage to the selected word line.
    Type: Application
    Filed: July 3, 2019
    Publication date: May 28, 2020
    Applicant: SK hynix Inc.
    Inventors: Ji Hyun SEO, Bong Yeol PARK, Hee Youl LEE, Han Soo JOO
  • Memory device and operating method thereof
    Patent number: 10665291
    Abstract: A memory device includes: a memory cell array including a plurality of memory cells respectively coupled to a plurality of word lines; a peripheral circuit configured to perform at least one program loop including applying a program voltage to selected memory cells coupled to a selected word line among the plurality of word lines and determining whether the selected memory cells have been completely programmed; and control logic configured to control the peripheral circuit to, while the program voltage is being applied to the selected word line, apply program control voltages of different levels to bit lines respectively coupled to memory cells in a first memory cell group among the selected memory cells and apply a program allowable voltage to bit lines respectively coupled to memory cells in a second memory cell group among the selected memory cells.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • MEMORY DEVICE INCLUDING VOLTAGE GENERATING CIRCUIT
    Publication number: 20200160915
    Abstract: Provided herein may be a memory device including a voltage generating circuit. The memory device may include a memory block including a channel layer formed between junctions included in a well, and a source select line, word lines, and drain select lines that are sequentially stacked on the well while enclosing the channel layer, a first voltage source configured to generate a first operating voltage to be applied to the well during a program operation or an erase operation, and a second voltage source configured to generate a second operating voltage to be applied to source lines that are coupled to the junctions during the program operation or the erase operation.
    Type: Application
    Filed: January 22, 2020
    Publication date: May 21, 2020
    Inventor: Hee Youl LEE
  • Semiconductor memory device and operating method thereof
    Patent number: 10658044
    Abstract: The semiconductor memory device includes a memory cell array, an address decoder, a switch, and a control logic. The memory cell array includes a plurality of memory blocks having a plurality of memory cells. The address decoder is connected to the memory cell array through row lines. The switch is connected non-memory lines among the row lines. The control logic controls operations of the address decoder and the switch. During an erase operation on memory cells included in a selected memory block among the plurality of memory blocks, the control logic controls the switch to precharge non-memory lines connected to an unselected memory block among the plurality of memory blocks and then float the non-memory lines connected to the unselected memory block.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • SEMICONDUCTOR DEVICE AND OPERATING METHOD OF THE SEMICONDUCTOR DEVICE
    Publication number: 20200143883
    Abstract: A semiconductor device and method of operating a semiconductor device, the semiconductor device includes memory strings coupled between a common source line and a bit line, and a peripheral circuit coupled to the memory strings through a plurality of word lines and a dummy word line, and configured to set bias of the word lines and the dummy word line before performing a read operation, wherein the peripheral circuit applies a first pass voltage to the word lines concurrently with applying an initial voltage lower than the first pass voltage to the dummy word line, and increases the first pass voltage and the initial voltage to a second pass voltage to set the bias of the word lines and the dummy word line.
    Type: Application
    Filed: May 28, 2019
    Publication date: May 7, 2020
    Applicant: SK hynix Inc.
    Inventors: Han Soo JOO, Ji Hyun SEO, Hee Youl LEE
  • MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    Publication number: 20200142606
    Abstract: Disclosed herein are a memory device and a method of operating the memory device. The memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell may a plurality of main memory blocks and a plurality of sub-memory blocks included in each of the main memory blocks. The peripheral circuit may perform a program operation on the main memory blocks or the sub-memory blocks, detect an amount of data loaded for the program operation, and output data amount information. The control logic may control the peripheral circuits so that, during the program operation, at least one memory block is selected from the main memory blocks or from the sub-memory blocks according to the data amount information and the program operation is performed on the selected memory block.
    Type: Application
    Filed: January 7, 2020
    Publication date: May 7, 2020
    Applicant: SK hynix Inc.
    Inventor: Hee Youl LEE
  • SEMICONDUCTOR DEVICE AND OPERATING METHOD OF THE SEMICONDUCTOR DEVICE
    Publication number: 20200126623
    Abstract: A method of operating a semiconductor device, the semiconductor device includes: a memory block including a plurality of word lines; and a control logic for performing a first program operation on first memory cells corresponding to a first word line among the plurality of word lines, performing the first program operation on second memory cells corresponding to a second word line adjacent to the first word line, performing a second program operation on the first memory cells, performing a dummy program operation on third memory cells corresponding to a third word line adjacent to the second word line, and performing the second program operation on the second memory cells.
    Type: Application
    Filed: June 11, 2019
    Publication date: April 23, 2020
    Applicant: SK hynix Inc.
    Inventor: Hee Youl LEE
  • Three-dimensional semiconductor device with top dummy cells and bottom dummy cells and operating method thereof
    Patent number: 10622040
    Abstract: Provided is a semiconductor device and an operating method thereof. The operating method of the semiconductor device includes performing a soft program operation on a top dummy cell and a bottom dummy cell, among dummy cells stacked in a vertical direction, by applying a first soft program voltage to a bottom dummy word line coupled to the bottom dummy cell and a second soft program voltage greater than the first soft program voltage to a top dummy word line coupled to the top dummy cell formed above the bottom dummy cell.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • MEMORY SYSTEM AND OPERATING METHOD THEREOF
    Publication number: 20200075103
    Abstract: A memory system includes: a plurality of dies including a plurality of memory blocks; and a memory controller for outputting a normal program command when a die including a selected memory block is a normal die having an electrical characteristic higher than or equal to a reference value in a program operation, and outputting a partial program command and a partial erase command when the die including the selected memory block is a low status die having an electrical characteristic lower than the reference value.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Applicant: SK hynix Inc.
    Inventors: Hee Youl LEE, Ji Ho PARK
  • Memory device including voltage generating circuit
    Patent number: 10580496
    Abstract: Provided herein may be a memory device including a voltage generating circuit. The memory device may include a memory block including a channel layer formed between Junctions included in a well, and a source select line, word lines, and drain select lines that are sequentially stacked on the well while enclosing the channel layer, a first voltage source configured to generate a first operating voltage to be applied to the well during a program operation or an erase operation, and a second voltage source configured to generate a second operating voltage to be applied to source lines that are coupled to the junctions during the program operation or the erase operation.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: March 3, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee