Abstract: A speech recognition apparatus includes a probability calculator configured to calculate phoneme probabilities of an audio signal using an acoustic model; a candidate set extractor configured to extract a candidate set from a recognition target list; and a result returner configured to return a recognition result of the audio signal based on the calculated phoneme probabilities and the extracted candidate set.

Abstract: Provided herein may be a semiconductor device and a method of operating a semiconductor device. The method may include: performing a first program operation on a selected memory cell using a first program pulse, a first bit line voltage, a first pre-verify voltage, and a first main verify voltage, with a first level difference between the first pre-verify voltage and the first main verify voltage; and performing a second program operation on the selected memory cell using a second program pulse, a second bit line voltage, a second pre-verify voltage, and a second main verify voltage, with a second level difference between the second pre-verify voltage and the second main verify voltage. The second level difference may be less than the first level difference, and the second bit line voltage may have a level higher than a level of the first bit line voltage.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may program shared page data on selected memory cells among the plurality of memory cells. The control logic may control, during the program operation on the selected memory cells, the peripheral circuit to program first partial data of the shared page data to memory cells coupled to a first word line among the selected memory cells, and to program second partial data of the shared page data to memory cells coupled to a second word line different from the first word line among the selected memory cells.

Abstract: A memory device and an operating method thereof are provided. The memory device includes: a plurality of memory strings connected between a bit and source lines, the plurality of memory strings connected to a first select line, a plurality of word lines, and a second select line, which are disposed between the bit line and the source line; a peripheral circuit for programming a selected memory cell included in a selected memory string among the memory strings; and control logic for controlling the peripheral circuit to program the selected memory cell. The control logic controls the peripheral circuit to apply a positive voltage to the bit and source lines, which are connected to an unselected memory string, before a program voltage is applied to a selected word line connected to the selected memory cell, and discharge the word lines and the first and second select lines at different times.

Abstract: An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

Abstract: A memory device includes word lines vertically stacked from a substrate, memory cells electrically connected to the word lines, a group controller configured to group the word lines into word line groups, and change the word line groups, based on electrical characteristics of the memory cells, and a voltage generator configured to store, in a voltage table, voltage values of operating voltages to be respectively applied to the word line groups.

Abstract: A memory device includes a memory cell array including a plurality of strings, a peripheral circuit coupled to the memory cell array and configured for sequentially performing a program voltage apply operation, a program verify operation, and a hole injection operation on the plurality of strings, and a control logic configured for controlling an operation of the peripheral circuit, wherein the control logic controls the operation of peripheral circuit to generate Gate Induced Drain Leakage (GIDL) at a channel under a select transistor of each of the plurality of strings during the hole injection operation.

Abstract: A method of operating a semiconductor memory device includes dummy-programming selected memory cells representing all the memory cells to be programmed for a programming operation. The method also includes determining as a first group of memory cells those selected memory cells having threshold voltages less than or equal to a reference threshold voltage and determining as a second group of memory cells those selected memory cells having threshold voltages greater than the reference threshold voltage. The method further includes program ling the selected memory cells by applying a first bit line voltage to the memory cells of the first group, applying a second bit line voltage different from the first bit line voltage to the memory cells of the second group, and applying a same program pulse to the memory cells of the first and second groups.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and peripheral circuits configured to sequentially program the pages. The memory device may include control logic configured to control the peripheral circuits such that a program voltage is applied to a word line coupled to a page selected from among the pages such that different pass voltages are applied to all or some word lines coupled to pages on which a program operation has been performed among unselected pages other than the selected page, and to word lines coupled to pages on which a program operation has not been performed among the unselected pages.

Abstract: Provided herein may be a memory device including a voltage generating circuit. The memory device may include a memory block including a channel layer formed between junctions included in a well, and a source select line, word lines, and drain select lines that are sequentially stacked on the well while enclosing the channel layer, a first voltage source configured to generate a first operating voltage to be applied to the well during a program operation or an erase operation, and a second voltage source configured to generate a second operating voltage to be applied to source lines that are coupled to the junctions during the program operation or the erase operation.

Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.

Abstract: A method of operating a semiconductor memory device includes dummy-programming selected memory cells representing all the memory cells to be programmed for a programming operation. The method also includes determining as a first group of memory cells those selected memory cells having threshold voltages less than or equal to a reference threshold voltage and determining as a second group of memory cells those selected memory cells having threshold voltages greater than the reference threshold voltage. The method further includes programming the selected memory cells by applying a first bit line voltage to the memory cells of the first group, applying a second bit line voltage different from the first bit line voltage to the memory cells of the second group, and applying a same program pulse to the memory cells of the first and second groups.

Abstract: A method of operating a semiconductor device, the semiconductor device includes: a memory block including a plurality of word lines; and a control logic for performing a first program operation on first memory cells corresponding to a first word line among the plurality of word lines, performing the first program operation on second memory cells corresponding to a second word line adjacent to the first word line, performing a second program operation on the first memory cells, performing a dummy program operation on third memory cells corresponding to a third word line adjacent to the second word line, and performing the second program operation on the second memory cells.

Abstract: A semiconductor device and method of operating a semiconductor device, the semiconductor device includes memory strings coupled between a common source line and a bit line, and a peripheral circuit coupled to the memory strings through a plurality of word lines and a dummy word line, and configured to set bias of the word lines and the dummy word line before performing a read operation, wherein the peripheral circuit applies a first pass voltage to the word lines concurrently with applying an initial voltage lower than the first pass voltage to the dummy word line, and increases the first pass voltage and the initial voltage to a second pass voltage to set the bias of the word lines and the dummy word line.

Abstract: A semiconductor device includes strings each having a plurality of memory cells. The strings are coupled between a common source line and a bit line. A method of operating the semiconductor device includes applying a pre-program voltage to a selected word line coupled to a selected memory cell and to an unselected word line coupled to an unselected memory cell adjacent to the selected memory cell among the plurality of memory cells. The method further includes applying a first program voltage to the selected word line.

Abstract: Disclosed are a semiconductor memory device, a memory system including the semiconductor memory device, and a method of operating the same. The memory system includes a controller receiving a host command and program data from a host, queueing a command in response to the host command, and generating grouping information by grouping a plurality of program states into two or more program groups, and a semiconductor memory device receiving a queued command, the program data, and the grouping information from the controller, performing a program operation, and sequentially programming the two or more program groups on the basis of the grouping information.

Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.

Abstract: A method of operating a semiconductor device, the semiconductor device includes: a memory block including a plurality of word lines; and a control logic for performing a first program operation on first memory cells corresponding to a first word line among the plurality of word lines, performing the first program operation on second memory cells corresponding to a second word line adjacent to the first word line, performing a second program operation on the first memory cells, performing a dummy program operation on third memory cells corresponding to a third word line adjacent to the second word line, and performing the second program operation on the second memory cells.

Abstract: A memory controller controlling a semiconductor memory device, the memory controller may comprises a host interface configured to receive a write request, from a host, to store data in the semiconductor memory device, a processor configured to generate a program command according to a type of the write request, a memory interface configured to provide the program command to the semiconductor memory device, wherein the type of the write request includes a first type write request and a second type write request, and wherein the first type write request requires faster write completion response than the second type write request.

Abstract: In a method for operating a semiconductor device, the method may include: sorting program states of a memory cell that stores multi-bit data into a plurality of groups; applying different bias voltages to bit lines corresponding to a selected group among the plurality of groups; applying a program voltage to a selected word line corresponding to the selected group; verifying whether each of selected memory cells corresponding to the selected word line is programmed to a respective target program state; applying an inhibition voltage to bit lines coupled to programmed memory cells; and selecting a next group to be programmed until the plurality of groups are programmed.