Abstract: An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.

Abstract: The memory has writable memory cells. In addition, it has a bit line pair which connects the memory cells MC to a differential sense amplifier. A control unit is used for precharging the bit lines in a plurality of steps before one of the memory cells is conductively connected to one of the bit lines for a read access operation. For a write access operation, the control unit carries out no more than some of the bit line precharging steps provided for a read access operation before the sense amplifier transfers data to the bit line pair.

Abstract: Providing an active signal that increases the gate overdrive voltage of the driver of a sense amplifier enables the use of smaller drivers. This facilitates more efficient layouts and/or smaller sense amplifiers, thereby reducing the chip size.

Abstract: An integrated memory includes word lines and bit lines intersecting each other at crossover points. The bit lines are combined into bit line pairs and the bit line pairs are interleaved by having at least one of the bit lines of one bit line pair disposed between the two bit lines of another bit line pair. 2-transistor/2-capacitor memory cells each have two 1-transistor/1-capacitor memory cells each disposed at a respective one of the crossover points. Each of the two 1-transistor/1-capacitor memory cells of the 2-transistor/2capacitor memory cells have a selection transistor connected to one of the two bit lines of a respective one of the bit line pairs and to at least one of the word lines. The selection transistors may be simultaneously activated for simultaneously accessing the two 1-transistor/1-capacitor memory cells of one of the 2-transistor/2-capacitor memory cell.

Abstract: An integrated memory is described that differs from conventional memories in that it has second amplifier unit, which are present in addition to first amplifier units that are disposed outside a cell array, for the output signals of a row decoder. The second amplifier units serve for amplifying the decoder signals driven onto the word lines by the first amplifier units and, in contrast to the latter, are disposed within the cell array. Interference caused by crosstalk, for example, on the word lines is suppressed as a result of the second amplifier units that are additionally present.

Abstract: The memory cell configuration is formed with hybrid memory cells. Individual bit line pairs are isolated from one another by a respective bit line from an adjacent bit line pair, so that the memory cells are arranged relative to one another with ¼ division. This means that intrinsically cohesive implantation mask parts without connection or corner regions can be used, which avoids implantation problems and still permits production of transistors with a different threshold voltage.

Abstract: The integrated memory has memory cells each with two transistors and two capacitors. Unlike conventional 2-transistor/2-capacitor memory cells, the plate electrodes of the capacitors are connected to different plate potentials.

Abstract: An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential.

Abstract: An arrangement of enhanced drivability transistors is disclosed herein which includes a plurality of conductor patterns, wherein the conductor patterns include ring-shaped portions which enclose device diffusion contacts and the ring-shaped portions form the gate conductors of insulated gate field effect transistors (IGFETs).

Abstract: An integrated memory having a first wiring plane with parallel conductor tracks running therein. A second wiring plane in the memory has segments running in it that are parallel to the conductor tracks. Word lines are each formed by a conductor track of a first type and by segments configured parallel to this conductor track. A conductor track of a second type is connected to a first supply line and to regions that are configured in a third wiring plane within the cell array.

Abstract: A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transfer device formed in a substantially electrically isolated mesa region extending over a substantial arc of the outer perimeter of the trench, a buried strap which conductively connects the transfer device to the storage capacitor, wherein the transfer device has a controlled conduction channel located at a position of the arc removed from the buried strap. Also disclosed herein are methods of forming a semiconductor memory cell and of forming groups of semiconductor memory cells.

Abstract: Reduced current consumption in a DRAM during standby mode is achieved by switching off the power source that is connected to, for example, the n-well.

Abstract: Disclosed is a semiconductor memory (18, 20, 100, 200) having a hierarchical bit line architecture including local bit lines (LBL.sub.1, LBL.sub.2) on a lower fabrication layer, coupled to memory cells (MC), and master bit lines (MBL) on a higher fabrication layer, each coupled to an associated sense amplifier (SA.sub.i). Local bit lines disposed in any given column are coupled to different numbers of memory cells, i.e., the local bit lines have different lengths (L1, L2) over the memory cells. A hybrid configuration is preferably employed in which one local bit line (LBL.sub.1) in a column is directly coupled via a switch (25.sub.1) to an associated sense amplifier, whereas the other local bit lines in the column (LBL.sub.2 -LBL.sub.4) are operatively coupled to the sense amplifier via the master bit line.

Abstract: Disclosed is a multiple bank semiconductor memory (40) (e.g., DRAM) capable of overlapping write/read operation to/from memory cells of different banks (MAa, MAb), and having a space efficient layout. Chip size is kept small by employing a single column decoder (44) for different banks, and a hierarchical column select line architecture, with bit line switches (59, 61, 63, 65) of different columns having a shared active area such as a common source region. In an illustrative embodiment, global column select lines (GCSL.sub.1 -GCSL.sub.(N/K)) selectively activate global bit line switches (67, 68) which are coupled to bank-specific data lines (LDQ, LDQ). Several bank bit line switches (59-66) are coupled to each global bit line switch, with two or more bank bit line switches of different columns having a shared diffusion region to realize a compact layout.

Abstract: An equalizer circuit for precharging a pair of bit lines in a dynamic random access memory circuit. The equalizer circuit includes a substantially T-shaped polysilicon gate portion oriented at an angle relative to the pair of bit lines. The angle is an angle other than an integer multiple of 90.degree.. The substantially T-shaped polysilicon gate portion includes first polysilicon area for implementing a gate of a first switch of the equalizer circuit. The first switch is coupled to a first bit line of the pair of bit lines and a second bit line of the pair of bit lines. The substantially T-shaped polysilicon gate portion also includes a second polysilicon area for implementing a gate of a second switch of the equalizer circuit. The second switch is coupled to the first bit line of the pair of bit lines and a precharge voltage source. The substantially T-shaped polysilicon gate portion further includes a third polysilicon area for implementing a gate of a third switch of the equalizer circuit.

Abstract: The semiconductor memory includes a memory cell array (10) of memory cells arranged in rows and columns, and a plurality of diagonal bit lines (BLP.sub.1 -BLP.sub.N) arranged in a pattern that changes horizontal direction along the memory cell array to facilitate access to said memory cells. The bit lines are arranged non-orthogonal to a plurality of dual word lines (WL.sub.1 -WL.sub.M), where each dual word line includes a master word line (MWL.sub.i) at a first layer and a plurality of local word lines (LWL.sub.1 -LWL.sub.X) at a second layer. The local word lines are connected to the master word line of a common row via a plurality of spaced electrical connections (29), e.g., electrical contacts in a "stitched" architecture, and each local word line is connected to plural memory cells (MC). The electrical connections run in substantially the same pattern along the memory cell array as the bit lines.

Abstract: A dynamic random access memory array having an array of memory cells. Individual cells of the array are addressable by a plurality of word lines and a plurality of bit lines. The memory cells are disposed in active areas of the array. The array of memory cells includes a first strip of memory cells. The dynamic random access memory array includes a lower metal layer and an upper metal layer disposed above the lower metal layer. The dynamic random access memory array further includes a dielectric layer disposed between the lower metal layer and the upper metal layer. There is further included a first bit line of the plurality of bit lines which includes a lower metal first bit line portion implemented in the lower metal layer. The lower metal first bit line portion is coupled to a first plurality of memory cells of the first strip of memory cells. The first bit line also includes an upper metal first bit line portion implemented in the upper metal layer.