Abstract: The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.

Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.

Abstract: A substrate semiconductor layer is attached to a carrier substrate through a sacrificial bonding material layer. A plurality of semiconductor dies included within continuous material layers are formed on a front side of the substrate semiconductor layer. Each of the continuous material layers continuously extends over areas of the plurality of semiconductor dies. A plurality of dicing channels is formed between neighboring pairs among the plurality of semiconductor dies by anisotropically etching portions of the continuous material layers located between neighboring pairs of semiconductor dies. The plurality of dicing channels extends to a top surface of the sacrificial bonding material layer. The sacrificial bonding material layer is removed selective to materials of surface portions of the plurality of semiconductor dies using an isotropic etch process. The plurality of semiconductor dies is singulated from one another upon removal of the sacrificial bonding material layer.

Abstract: A solid state drive is disclosed including a planar array of semiconductor devices for use in a datacenter, and a system for cooling the planar array of semiconductor devices. The semiconductor devices may be arranged in a grid pattern, spaced apart from each other so as to define rows and columns of flow pathways, or cooling tunnels, around and between the semiconductor devices.

Abstract: The present technology relates to a semiconductor device. The semiconductor device comprises: a plurality of dies stacked on top of each other, each of the dies comprising a first major surface, an IO conductive pattern on the first major surface and extended to a minor surface substantially perpendicular to the major surfaces to form at least one IO electrical contact on the minor surface, and the plurality of dies aligned so that the corresponding minor surfaces of all dies substantially coplanar with respect to each other to form a common flat sidewall, and a plurality of IO routing traces formed over the sidewall and at least partially spaced away from the sidewall. The plurality of IO routing traces are spaced apart from each other in a first direction on the sidewall, and each of IO routing traces is electrically connected to a respective IO electrical contact and extended across the sidewall in a second direction substantially perpendicular to the first direction on the sidewall.

Abstract: A semiconductor device is disclosed including a stack of wafers having a densely configured 3D array of memory die. The memory die on each wafer may be arranged in clusters, with each cluster including an optical module providing an optical interconnection for the transfer of data to and from each cluster.

Abstract: A substrate semiconductor layer is attached to a carrier substrate through a sacrificial bonding material layer. A plurality of semiconductor dies included within continuous material layers are formed on a front side of the substrate semiconductor layer. Each of the continuous material layers continuously extends over areas of the plurality of semiconductor dies. A plurality of dicing channels is formed between neighboring pairs among the plurality of semiconductor dies by anisotropically etching portions of the continuous material layers located between neighboring pairs of semiconductor dies. The plurality of dicing channels extends to a top surface of the sacrificial bonding material layer. The sacrificial bonding material layer is removed selective to materials of surface portions of the plurality of semiconductor dies using an isotropic etch process. The plurality of semiconductor dies is singulated from one another upon removal of the sacrificial bonding material layer.

Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.

Abstract: A device may include a fan-out structure that has a plurality of integrated circuits. The integrated circuits may be of different types, such as by being configured differently or configured to perform different functions. The fan-out structure may be coupled to another integrated circuit structure, such as a die stack. For example, the fan-out structure may be coupled to a top surface or a bottom surface of the integrated circuit structure, or may otherwise be disposed within a vertical profile defined by the integrated circuit structure. Horizontally-extending and vertically-extending paths may be disposed in between and around the combined fan-out structure and integrated circuit structure to enable the integrated circuits of the two structures to communicate.

Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.

Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.

Abstract: A semiconductor device is disclosed mounted at an angle on a signal carrier medium such as a printed circuit board. The semiconductor device includes a stack of semiconductor die stacked in a stepped offset configuration. The die stack may then be encapsulated in a block of molding compound. The molding compound may then be singulated with slanted cuts along two opposed edges. The slanted edge may then be drilled to expose the electrical contacts on each of the semiconductor die. The slanted edge may then be positioned against a printed circuit board having solder or other conductive bumps so that the conductive bumps engage the semiconductor die electrical contacts in the drilled holes. The device may then be heated to reflow and connect the electrical contacts to the conductive bumps.

Abstract: A USB device is disclosed including an integrated memory module and USB connector. Integration of the memory module with the USB connector according to the present technology provides a USB device with a compact footprint and efficient heat transfer to a host device in which the USB device is used.

Abstract: A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.

Abstract: A USB device is disclosed including an integrated memory module and USB connector. Integration of the memory module with the USB connector according to the present technology provides a USB device with a compact footprint and efficient heat transfer to a host device in which the USB device is used.

Abstract: A semiconductor device is disclosed including a stack of wafers having a densely configured 3D array of memory die. The memory die on each wafer may be arranged in clusters, with each cluster including an optical module providing an optical interconnection for the transfer of data to and from each cluster.

Abstract: A solid state drive is disclosed including a planar array of semiconductor devices for use in a datacenter, and a system for cooling the planar array of semiconductor devices. The semiconductor devices may be arranged in a grid pattern, spaced apart from each other so as to define rows and columns of flow pathways, or cooling tunnels, around and between the semiconductor devices.

Abstract: A semiconductor device vertically mounted on a medium such as a printed circuit board, and a method of its manufacture, are disclosed. The semiconductor device includes a stack of semiconductor die having contact pads which extend to an active edge of the die aligned on one side of the stack. The active edges of the die are affixed to the PCB and the contact pads at the active edge are electrically coupled to the PCB. This configuration provides an optimal, high density arrangement of semiconductor die in the device, where a large number of semiconductor die can be mounted and electrically coupled directly to the PCT, without a substrate, without staggering the semiconductor die, and without using wire bonds.

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.

Abstract: A semiconductor device is disclosed including at least first and second vertically stacked and interconnected semiconductor packages. Signal communication between the second semiconductor package and a host device occurs through the first semiconductor package.