Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

Abstract: Technologies for conformal power delivery structures near high-speed signal traces are disclosed. In one embodiment, a dielectric layer may be used to keep a power delivery structure spaced apart from high-speed signal traces, preventing deterioration of signals on the high-speed signal traces due to capacitive coupling to the power delivery structure.

Abstract: Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

Abstract: An inductor structure, a package substrate, an integrated circuit device, an integrated circuit device assembly and a method of fabricating the inductor structure. The inductor structure includes: an electrically conductive body; and a magnetic structure including a non-electrically-conductive magnetic material, wherein: one of the magnetic structure or the electrically conductive body wraps around another one of the magnetic structure or the electrically conductive body to form the inductor structure therewith; and at least one of the electrically conductive body or the magnetic structure has a granular microstructure including randomly distributed particles presenting substantially non-linear particle-to-particle boundaries with one another.

Abstract: A embedded passive structure, a microelectronic system, and an integrated circuit device assembly, and a method of forming the embedded passive structure. The embedded passive structure includes a base layer; a passive device attached to the base layer; a first power plane comprising metal and adjacent an upper surface of the base layer, the first power plane having a portion electrically coupled to a terminal of the passive device, wherein an upper surface of a combination of the first power plane and the passive device defines a recess; a second power plane comprising metal, the second power plane at least partially within the recess and having a lower surface that conforms with the upper surface of the combination; and a liner including a dielectric layer between the first power plane and the second power plane.

Abstract: A conformal power delivery structure, a three-dimensional (3D) stacked die assembly, a system including the 3D stacked die assembly, and a method of forming the conformal power delivery structure. The power delivery structure includes a package substrate, a die adjacent to and electrically coupled to the package substrate; a first power plane adjacent the upper surface of the package substrate and electrically coupled thereto; a second power plane at least partially within recesses defined by the first power plane and having a lower surface that conforms with the upper surface of the first power plane; and a dielectric material between the first power plane and the second power plane.

Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

Abstract: Embodiments may relate to a microelectronic package that includes a radio frequency (RF) chip coupled with a die by interconnects with a first pitch. The RF chip may further be coupled with a waveguide of a package substrate by interconnects with a second pitch that is different than the first pitch. The RF chip may facilitate conveyance of data to the waveguide as an electromagnetic signal with a frequency greater than approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.

Abstract: Embodiments may relate to a multi-chip microelectronic package that includes a first die and a second die coupled to a package substrate. The first and second dies may have respective radiative elements that are communicatively coupled with one another such that they may communicate via an electromagnetic signal with a frequency at or above approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.

Abstract: Apparatus and methods of manufacture are disclosed. In one example the apparatus includes a first substrate that has a first surface, a first optical waveguide that is at or near the first surface of the first substrate, a second substrate that has a second surface. The second substrate is coupled to the first substrate at an interface. The apparatus also has a photonic integrated circuit (PIC) with a portion at or near the second surface. The PIC is in alignment with and optically coupled to the first optical waveguide across the interface.

Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

Abstract: An integrated circuit package having an electronic interposer comprising an upper section, a lower section and a middle section, a die side integrated circuit device electrically attached to the upper section of the electronic interposer, a die side heat dissipation device thermally contacting the die side integrated circuit device, a land side integrated circuit device electrically attached to the lower section of the electronic interposer, and a land side heat dissipation device thermally contacting the at least one die side integrated circuit device. The upper section and the lower section may each have between two and four layers and the middle section may be formed between the upper section and the lower section, and comprises up to eight layers, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.

Abstract: Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.

Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

Abstract: A device package and a method of forming the device package are described. The device package includes a substrate having a ground plane and dies disposed on the substrate. The dies are electrically coupled to the substrate with solder balls or bumps surrounded by an underfill layer. The device package has a mold layer disposed over and around the dies, the underfill layer, and the substrate. The device package further includes an additively manufactured electromagnetic interference (EMI) shield layer disposed on an outer surface of the mold layer. The additively manufactured EMI shield layer is electrically coupled to the ground plane of the substrate. The outer surface of the mold layer may include a topmost surface and one or more sidewalls that are covered with the additively manufactured EMI shield layer. The additively manufactured EMI shield may include a first and second additively manufactured EMI shield layers and an additively manufactured EMI shield frame.