Patents by Inventor Henning Braunisch

Henning Braunisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10304686
    Abstract: Embodiments include devices and methods, including a method for processing a substrate. The method includes providing a substrate including a first portion and a second portion, the first portion including a feature, the feature including an electrically conductive region, the second portion including a dielectric surface region. The method also includes performing self-assembled monolayer (SAM) assisted structuring plating to form a structure comprising a metal on the dielectric surface region, the feature being formed using a process other than the SAM assisted structuring plating used to form the structure, and the structure being formed after the feature. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Sasha N. Oster, Fay Hua, Telesphor Kamgaing, Adel A. Elsherbini, Henning Braunisch, Johanna M. Swan
  • Publication number: 20190150291
    Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Brandon M. RAWLINGS, Henning BRAUNISCH
  • Publication number: 20190149243
    Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, where the transceiver is configured to receive a data stream, convert the data stream to a quadrature amplitude modulation (QAM) mapping/shaping signal, where the QAM mapping/shaping signal is a frequency component of the data stream, convert the QAM mapping/shaping signal to a Hilbert transform signal, where the Hilbert transform signal includes a reverse order of an in-phase component of the QAM mapping/shaping signal and a reverse order of a quadrature component of the QAM mapping/shaping signal, convert the Hilbert transform signal to a QAM mapping/shaping signal, where the QAM mapping/shaping signal is a single sideband (SSB) time domain mm wave signal, where the SSB time domain mm wave signal is the Hilbert transform signal converted to a time domain signal, and communicate the SSB time domain mm wave signal over a waveguide using a waveguide interconnect.
    Type: Application
    Filed: December 18, 2018
    Publication date: May 16, 2019
    Applicant: Intel Corporation
    Inventors: Hyung-Jin Lee, Cho-ying Lu, Henning Braunisch, Telesphor Kamgaing, Georgios Dogiamis, Richard Dischler
  • Publication number: 20190115951
    Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 18, 2019
    Applicant: Intel Corporation
    Inventors: Henning Braunisch, Georgios Dogiamis, Jeff C. Morriss, Hyung-Jin Lee, Richard Dischler, Ajay Balankutty, Telesphor Kamgaing, Said Rami
  • Publication number: 20190097293
    Abstract: There is disclosed in one example an electromagnetic wave launcher apparatus, including: an interface to an electromagnetic waveguide; a first launcher configured to launch a high-frequency electromagnetic signal onto a first cross-sectional portion of the waveguide; and a second launcher configured to launch a lower-frequency electromagnetic signal onto a second cross-sectional portion of the waveguide.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Adel A. Elsherbini, Henning Braunisch, Gilbert W. Dewey, Telesphor Kamgaing, Hyung-Jin Lee, Johanna M. Swan
  • Publication number: 20190096798
    Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Arnab Sarkar, Arghya Sain, Kristof Darmawikarta, Henning Braunisch, Prashant D. Parmar, Sujit Sharan, Johanna M. Swan, Feras Eid
  • Publication number: 20190089409
    Abstract: Embodiments may relate to a transceiver chip. The transceiver chip may include a substrate that has a first transceiver component and a second transceiver component positioned therein. The transceiver chip may further include a well material that is positioned between the first transceiver component and the second transceiver component. The well material may mitigate cross-talk between the first transceiver component and the second transceiver component. Other embodiments may be described or claimed.
    Type: Application
    Filed: November 20, 2018
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Telesphor Kamgaing, Georgios Dogiamis, Henning Braunisch, Hyung-Jin Lee, Richard Dischler
  • Publication number: 20190081705
    Abstract: There is disclosed in one example a communication apparatus, including: a local data interface; a data encoder to encode a transmission into n millimeter to terahertz-band transmission components, wherein n?2, each transmission component having an independent mode of each other transmission component; and a plurality of n launchers to launch the transmission components onto n closely-bundled waveguides, wherein the closely-bundled waveguides are not shielded from one another.
    Type: Application
    Filed: November 2, 2018
    Publication date: March 14, 2019
    Applicant: Intel Corporation
    Inventors: Henning Braunisch, Adel A. Elsherbini, Georgios Dogiamis, Telesphor Kamgaing, Aleksandar Aleksov, Johanna M. Swan
  • Patent number: 10187998
    Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Brandon M. Rawlings, Henning Braunisch
  • Patent number: 10186465
    Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Adel A. Elsherbini, Henning Braunisch, Yidnekachew S. Mekonnen, Krishna Bharath, Mathew J. Manusharow, Aleksandar Aleksov, Nathan Fritz
  • Publication number: 20180328957
    Abstract: Embodiments of the invention include a microelectronic device having a sensing device and methods of forming the sensing device. In an embodiment, the sensing device includes a mass and a plurality of beams to suspend the mass. Each beam comprises first and second conductive layers and an insulating layer positioned between the first and second conductive layers to electrically isolate the first and second conductive layers. The first conductive layer is associated with drive signals and the second conductive layer is associated with sense signals of the sensing device.
    Type: Application
    Filed: December 17, 2015
    Publication date: November 15, 2018
    Inventors: Feras EID, Henning BRAUNISCH, Georgios C. DOGIAMIS, Sasha N. OSTER
  • Publication number: 20180288868
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 4, 2018
    Inventors: Adel A. ELSHERBINI, Matthew MANUSHAROW, Krishna BHARATH, Zhichao ZHANG, Yidnekachew S. MEKONNEN, Aleksandar ALEKSOV, Henning BRAUNISCH, Feras EID, Javier SOTO
  • Publication number: 20180286687
    Abstract: Embodiments include devices and methods, including a method for processing a substrate. The method includes providing a substrate including a first portion and a second portion, the first portion including a feature, the feature including an electrically conductive region, the second portion including a dielectric surface region. The method also includes performing self-assembled monolayer (SAM) assisted structuring plating to form a structure comprising a metal on the dielectric surface region, the feature being formed using a process other than the SAM assisted structuring plating used to form the structure, and the structure being formed after the feature. Other embodiments are described and claimed.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Sasha N. OSTER, Fay HUA, Telesphor KAMGAING, Adel A. ELSHERBINI, Henning BRAUNISCH, Johanna M. SWAN
  • Patent number: 10054737
    Abstract: Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: August 21, 2018
    Assignee: INTEL CORPORATION
    Inventors: Mauro J Kobrinsky, Henning Braunisch, Shawna M. Liff, Peter L. Chang, Bruce A. Block, Johanna M. Swan
  • Publication number: 20180233431
    Abstract: Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 16, 2018
    Inventors: Adel A. ELSHERBINI, Henning BRAUNISCH, Brandon M. RAWLINGS, Aleksandar ALEKSOV, Feras EID, Javier SOTO
  • Publication number: 20180226310
    Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 9, 2018
    Inventors: Feras EID, Adel A. ELSHERBINI, Henning BRAUNISCH, Yidnekachew MEKONNEN, Krishna BHARATH, Mathew J. MANUSHAROW, Aleksandar ALEKSOV, Nathan FRITZ
  • Publication number: 20180182707
    Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Adel A. Elsherbini, Henning Braunisch, Javier Soto Gonzalez, Shawna M. Liff
  • Patent number: 9992859
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • Publication number: 20180145031
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Application
    Filed: January 19, 2018
    Publication date: May 24, 2018
    Inventors: Henning BRAUNISCH, Chia-Pin CHIU, Aleksandar ALEKSOV, Hinmeng AU, Stefanie M. LOTZ, Johanna M. SWAN, Sujit SHARAN
  • Patent number: 9875969
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: January 23, 2018
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Stefanie M. Lotz, Johanna M. Swan, Sujit Sharan