Abstract: A mask is configured for projecting a structure pattern onto a semiconductor substrate in an exposure unit. The exposure unit has a minimum resolution limit for projecting the structure pattern onto the semiconductor substrate. The mask has a substrate, at least one raised first structure element on the substrate which has a lateral extent which is at least the minimum lateral extent that can be attained by the exposure unit, a configuration second raised structure elements which are arranged in an area surrounding the at least one first structure element on the substrate in the form of a matrix with a row spacing and a column spacing, whose shape and size are essentially identical to one another, and which have a respective lateral extent that is less than the minimum resolution limit of the exposure unit.

Abstract: Tolerances to be communicated to the manufacturer for a photomask fabrication process that are assigned as desired values of feature sizes to be realized on the photomask, are freed of restrictions by predefining, for a first feature size, a first desired value and a first tolerance assigned to the first desired value. The real discrepancy between the first feature size and the first desired value is taken into account when predefining desired values assigned to the further feature sizes to be provided on the photomask. As a result, a value which corresponds to a first approximation to the permitted feature size tolerance on the semiconductor wafer is provided for the tolerances of the desired values.

Abstract: The method of dynamically monitoring a reticle includes preventively macro monitoring and defect inspecting with regard to mechanical loading, including particle deposits or electrostatically induced damage, and energy load, including the associated changes to the reticle material and surface characteristics. Different surface distributions of the absorber layer as well as characteristics of the exposure system, such as N2 purging of the projection lens/reticle area in order to reduce contamination and recrystallization on optically active surfaces are considered.

Abstract: A reticle control system and method in which each reticle is unambiguously assigned a structured reticle data set, and the content of each reticle data set is automatically changed and/or supplemented depending on use of the associated reticle in the semiconductor component production process for which the reticle was produced. The reticle data set is used to identify and control the reticles over the entire production sequence. The ability to change or supplement the reticle data sets facilitates progressively storing production-dictated information related to the use of the associated reticles, thereby enabling effective control of the reticles in the production process.

Abstract: A method of inspecting a mask or reticle, the mask or reticle being provided with a pattern to be transferred onto a semiconductor wafer, the pattern having a defect, includes the step of creating a plurality of logical zones and uniquely associating each of said logical zones with a surface area of said pattern. Then, an inspection rule representing a characteristic sensitivity for detecting a defect is associated with each of said logical zones. An image of said pattern is then recorded and compared with a reference image of an ideal pattern for locating a defect within said pattern. One of said logical zones is then identified with said located defect and that inspection rule which is associated with said identified logical zone is retrieved from a memory. The inspection rule is then applied to a characteristic of said defect for determining, whether said defect is to be repaired. A signal can be issued in response to said determination.

Abstract: The invention relates to a method for production of contacts on a wafer, preferably with the aid of a lithographic process. The preferred embodiment provides a method which overcomes the disadvantages of the complex point/hole lithography process, and which avoids any increase in the process complexity. This method is achieved in that a strip structure extending over two layers is used to structure the contacts. The strip structure in the first layer is rotated at a predetermined angle with respect to the strip structure in the second layer, and the contacts are formed in the mutually overlapping areas of the strip structures in the two layers.

Abstract: A mask is configured for projecting a structure pattern onto a semiconductor substrate in an exposure unit. The exposure unit has a minimum resolution limit for projecting the structure pattern onto the semiconductor substrate. The mask has a substrate, at least one raised first structure element on the substrate which has a lateral extent which is at least the minimum lateral extent that can be attained by the exposure unit, a configuration second raised structure elements which are arranged in an area surrounding the at least one first structure element on the substrate in the form of a matrix with a row spacing and a column spacing, whose shape and size are essentially identical to one another, and which have a respective lateral extent that is less than the minimum resolution limit of the exposure unit.

Abstract: A measuring position for finding a structural element for measuring a characteristic dimension, for instance, the critical dimension CD, which element is about to be formed on a mask, is inserted as second data information into an exchange file containing the circuit layout in a hierarchical configuration of first data information or cells representing the structural elements. To prevent the second data information, which are virtual structural elements, from being incorporated in the control instructions for mask exposure, like the first data information, as structural elements that are to be formed, the second data information does not include an allocation of a geometric shape to the measuring position, or a shape that is allocated thereto has the transparency of the background, so that there is no contrast during the exposure. The second data information can be inserted as allocated to a plane that is not converted into a control instruction.

Abstract: An exposure mask has a phase mask and a phase-shifting dummy structure. The exposure mask can be repaired with regard to defects in the dummy structure. For that purpose, repair structures are applied on the exposure mask substrate material which have a lower phase shift compared to the dummy structures. The repair structure is preferably produced from carbon, the carbon being applied in a suitable layer thickness such that the repair structure no longer permits any transmission. In a preferred embodiment, the repair structure is arranged laterally offset with respect to the defect in the dummy structure.

Abstract: A method for generating mask layout data for lithography simulation includes prescribing original data defining an original layout of a mask and determining a deviation between the original layout and a subsequent layout of a mask derived from said original layout. On the basis of this deviation, new data defining a new layout is calculated. This new layout is more similar to the subsequent layout that it is to the original layout.

Abstract: A method for producing circuit structures on a semiconductor substrate is described. Photoresist structures are formed, which define functional circuit structures and dummy circuit structures, whereby the dummy circuit structures which are smaller than a minimum structural size are joined to an additional second dummy circuit structure. The additional circuit structure is provided in such a way that the minimum structural size, which is determined by a smallest required joint surface of the photoresist on the substrate, is exceeded. A semiconductor circuit is also provided, which includes functional circuit structures and dummy circuit structures, the dummy circuit structures being joined to the additional dummy circuit structures.

Abstract: A method of fabricating a semiconductor device is outlined in FIG. 3. An ideal (or desired) pattern of a layer of the semiconductor device is designed (305). A first pass corrected pattern is then derived by correcting the ideal patterns for major effects, e.g., aerial image effects (315, 320). A second pass corrected pattern is then derived by correcting the first pass corrected patterns for remaining errors (304). The second pass corrected pattern can be used to build a photomask (345). The photomask can then be used to produce a semiconductor device, such a memory chip or logic chip (350).

Abstract: An exposure mask has a phase mask and a phase-shifting dummy structure. The exposure mask can be repaired with regard to defects in the dummy structure. For that purpose, repair structures are applied on the exposure mask substrate material which have a lower phase shift compared to the dummy structures. The repair structure is preferably produced from carbon, the carbon being applied in a suitable layer thickness such that the repair structure no longer permits any transmission. In a preferred embodiment, the repair structure is arranged laterally offset with respect to the defect in the dummy structure.

Abstract: There is provided a method for Optical Proximity Correction (OPC) of a semiconductor device. The method includes the step of pre-sorting the shapes and/or the shape edges into groups based on pre-defined criteria. Different regions of interest are applied to at least some of the shapes and the shape edges, based on which of the groups the at least some of the shapes and the shape edges are pre-sorted into. The pre-defined criteria may include: properties or labels associated with the shapes and/or the shape edges during a design process of the semiconductor device; geometric properties of the shapes and/or the shape edges; structural properties of an overall design of the semiconductor device; and the shapes and/or the shape edges for which a larger region of interest is required.

Abstract: A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion.

Abstract: A method, and a system for employing the method, for providing a modified optical proximity correction (OPC) for correcting distortions of pattern lines on a semiconductor circuit wafer. The method comprises producing a mask having one or more pattern regions, and producing the semiconductor circuit wafer from the mask. The pattern regions include one or more non-edge pattern regions located adjacent to other of the non-edge pattern regions on the mask. The pattern regions further include one or more edge pattern regions located at or near an area on the mask not having the other non-edge pattern regions. The edge pattern regions have widths calculated to minimize the variance in dimensions between one or more pattern lines on the semiconductor circuit wafer formed from them and one or more pattern lines on the semiconductor circuit wafer formed from the non-edge pattern regions.

Abstract: A semiconductor device can be fabricated using a photomask that has been modified using an assist feature design method (see e.g., FIG. 4A) based on normalized feature spacing. Before the device can be fabricated, a layout of original shapes is designed (402). For at least some of the original shapes, the width of the shape and a distance to at least one neighboring shape are measured (404). A modified shape can then be generated by moving edges of the original shape based on the width and distance measurements (406). This modification can be performed on some or all of the original shapes (408). For each of the modified shapes, a normalized space and correct number of assist features can be computed (410). The layout is then modified by adding the correct number of assist features in a space between the modified shape and the neighboring shape (412). This modified layout can then be used in producing a photomask, which can in turn be used to produce a semiconductor device.

Abstract: A method for generating mask layout data for lithography simulation includes prescribing original data defining an original layout of a mask and determining a deviation between the original layout and a subsequent layout of a mask derived from said original layout. On the basis of this deviation, new data defining a new layout is calculated. This new layout is more similar to the subsequent layout that it is to the original layout.

Abstract: A method for producing circuit structures on a semiconductor substrate is described. Photoresist structures are formed, which define functional circuit structures and dummy circuit structures, whereby the dummy circuit structures which are smaller than a minimum structural size are joined to an additional second dummy circuit structure. The additional circuit structure is provided in such a way that the minimum structural size, which is determined by a smallest required joint surface of the photoresist on the substrate, is exceeded. A semiconductor circuit is also provided, which includes functional circuit structures and dummy circuit structures, the dummy circuit structures being joined to the additional dummy circuit structures.

Abstract: A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.