Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.

Abstract: A chip includes a memory array and a refresh counter. The refresh counter is configured to receive refresh trigger signals. The refresh counter is configured or configurable to initiate a refresh of the memory array only once per i of the received refresh trigger signals where i is a number greater than 1.

Abstract: A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.

Abstract: An electronic device provides a stack of semiconductor chips. A redistribution layer of a first semiconductor chip is arranged at the bottom of the stack. The redistribution layer of the first semiconductor chip comprises external pads.

Abstract: A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.

Abstract: A memory circuit includes multiple memory chips configured to store data and disposed in at least one stack. The memory circuit includes multiple ports configured to receive and transmit control signals and data to and from the memory chips and to supply energy to the memory circuit. The memory circuit includes a housing accommodating the multiple memory chips and the multiple ports.

Abstract: Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.

Abstract: The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.

Abstract: The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.

Abstract: A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.

Abstract: The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.

Abstract: A method for operating a memory apparatus which comprises at least two memory devices, each memory device containing at least one bank, comprising: activation of at least one word line in at least one bank on the basis of a row activation command; storage of bank information, the bank information indicating which banks per memory device contain a word line activated by the row activation command; reading/writing of memory contents from/to banks with activated word lines on the basis of the bank information.

Abstract: A memory apparatus includes at least two memory devices, each memory device including at least one memory bank. A method of operating the memory apparatus includes receiving a row activation command generated by a memory controller, wherein the row activation command includes a bank address. The method also includes activating a word line in a bank of one of the memory devices based on the row activation command, wherein the bank address is used to select the memory device.

Abstract: Embodiments of the invention relate to an integrated circuit comprising at least one functional unit configured to operate at a first clock frequency. The integrated circuit also comprises at least one first interconnect originating from a contact pad and leading to at least one frequency divider configured to receive a clock signal having a second frequency and generate one or more clock signals to operate the functional unit at the first frequency. The integrated circuit further comprises at least one second interconnect coupling an output of the frequency divider and an input of the functional unit, wherein a total length of the second wired interconnect is less than a total length of the first wired interconnects.

Abstract: An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.

Abstract: Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.

Abstract: Stackable circuit devices include mechanical and electrical connection elements that are optionally disengageable and disconnectable. The mechanical connection elements comprise pairs of complementary male and female plug-in engagement elements respectively arranged at opposite matching positions on top and bottom faces of each device package. The male and female plug-in engagement elements provide a mutual plug-in engagement. The electrical connection elements comprise a plurality of first and second complementary contact elements respectively arranged in opposite and matching positions on either the top or bottom face of each device package. When the circuit devices are stacked, the first contact elements are respectively configured to provide an electrical connection to a complementary matching second contact element of an adjacently plugged in circuit device.

Abstract: Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.

Abstract: A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from a first and second set of memory chips. Transfer of an internal packet data from the control device to memory takes place such that a first record is stored in a second set of memory chips and additional records are stored in the first set of memory chips. In preferred embodiments, data is allocated in the second set of memory chips such that at least one additional transfer step takes place to the second set of memory chips compared with transfers to the first set of memory chips. In the additional transfer step(s), the first set of memory chips is masked from receiving data.

Abstract: A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.