Abstract: An arrangement of semiconductor memory devices includes a first semiconductor memory device and a second semiconductor memory device. The arrangement of semiconductor memory devices also has a flexible substrate. A first electrically conductive conductor track is arranged in the flexible substrate. At least one first contact of the flexible substrate is coupled to the at least one second contact of the second semiconductor memory device through the first electrically conductive conductor track. A second electrically conductive conductor track is arranged in the flexible substrate.

Abstract: Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.

Abstract: Embodiments relates to a memory device, comprising a plurality of memory cells, said memory cells being addressable by a plurality of addresses, an interface for reading and/or writing data from a host system to said memory device, said interface comprising at least an address bus and a clock signal line, said address bus being configured to transmit a first part of an address at the leading edge of said clock signal and a second part of an address at the trailing edge of said clock signal.

Abstract: The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.

Abstract: A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.

Abstract: The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.

Abstract: An integrated device comprising a storage location, wherein data stored in the storage location is repeatedly refreshed with a first predetermined refresh rate during a first period of time. The first period of time provides a first predetermined duration. After the end of the first period of time, the data is repeatedly refreshed with a second predetermined refresh rate.

Abstract: The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.

Abstract: A memory device comprising at least a plurality of memory cells and a memory control unit to read and write user data to said memory cells is provided. The memory device comprises further a monitoring unit for retrieving a plurality of data concerning the memory device and a comparing unit. The comparing unit receives an output signal of the monitoring unit and is configured to compare the plurality of retrieved data with a plurality of reference values.

Abstract: A memory device includes at least two DRAM memory modules, at least one external ECC module, and a memory controller. The external ECC module provides the memory modules with ECC functionality. Each memory module is connected to the memory controller via a respective memory channel. The external ECC modules are connected to the memory controller via a common ECC channel. Each external ECC module is assigned to a group of the memory modules. The memory modules of one group with respective ECC modules are synchronously operated by the memory controller.

Abstract: A method for operating a memory apparatus which comprises at least two memory devices, each memory device containing at least one bank, comprising: activation of at least one word line in at least one bank on the basis of a row activation command; storage of bank information, the bank information indicating which banks per memory device contain a word line activated by the row activation command; reading/writing of memory contents from/to banks with activated word lines on the basis of the bank information.

Abstract: An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection and the memory circuit is deactivated.

Abstract: A memory apparatus includes at least two memory devices, each memory device including at least one memory bank. A method of operating the memory apparatus includes receiving a row activation command generated by a memory controller, wherein the row activation command includes a bank address. The method also includes activating a word line in a bank of one of the memory devices based on the row activation command, wherein the bank address is used to select the memory device.

Abstract: An input receiver circuit is provided for receiving a noisy high-speed input signal and for generating a plurality of output signals that can be processed at a low acquisition speed compared to the speed of the high-speed input signal. The input receiver circuit includes an input for receiving the high-speed input signal (data), a plurality of integration elements and a switch for connecting the input to one of the plurality of integration elements for integrating the high-speed input signal. The input receiver circuit further includes a plurality of means for receiving one of the integrated high-speed input signals at a time and for outputting one of the plurality of output signals at a time, and a controller for controlling the switch.

Abstract: In a semiconductor memory system, the memory chips are linked to a memory module in a shared loop forward architecture and connected in a point-to-point connection to a memory controller. Each memory chip includes a high-speed interface circuit including: a read and write data/command-and-address signal re-driver/transmitter path for re-driving serial read data and write data/command-and-address signals not destined for the semiconductor memory chip; and a main signal path which includes a serial-to-parallel converter and a synchronizer for serial-to-parallel converting and synchronizing with a reference clock signal write data/command-and-address signals destined for the semiconductor memory chip as well as a parallel-to-serial converter for parallel-to-serial converting read data signals read from a memory core of the memory chips, and a switch for inserting the parallel-to-serial converted read data signals into the re-driver/transmitter path.

Abstract: A memory module includes a module circuit board, an amplifier circuit disposed on the module circuit board for amplifying an input signal, and a memory component to store a data item, wherein the memory component is disposed on the module circuit board. The amplifier circuit includes an input to receive a data signal and an output to provide an amplified data signal. The memory component comprises an input to receive the amplified data signal, wherein the data item is stored in the memory component in dependence on a level of the received amplified data signal.

Abstract: A buffer chip having a first data interface for receiving a data item which is to be written and for sending a data item which has been read, having a conversion unit for parallelizing the received data item and for serializing the data item which is to be sent, having a second data interface for writing the parallelized data item to a memory arrangement via a memory data bus and for receiving the data item read from the memory arrangement via the memory data bus; having a write buffer storage for buffer-storing the data item which is to be written, having a control unit in order, after reception of a data item which is to be written via the first data interface in line with a write command, to interrupt the data from being written from the write buffer storage via the second data interface upon a subsequent read command.

Abstract: A semiconductor component includes an integrated semiconductor chip and a chip housing. The chip housing has first, second, third and fourth conductor tracks that connect input and output connections of the semiconductor chip to external contact connections on the underside and top side of the chip housing in such a way that a loop back interconnection of a plurality of semiconductor components stacked one on top of another is made possible without subsequent structural alterations to the chip housings thereof.

Abstract: A semiconductor device having a stacked arrangement of a substrate and a first chip and a second chip is disclosed. In one embodiment, the first chip is arranged with a lower face on an upper face of the substrate; the second chip with a lower face on an upper face of the first chip, whereby a partial area of the upper face of the first chip that is adjacent to an edge of the first chip is uncovered by the second chip; a fifth wire contact pad is arranged on the uncovered area of the upper face of the first chip; a first bonding wire is arranged that is connected with a first wire contact pad of the substrate and the fifth wire contact pad of the first chip.

Abstract: Semiconductor memory modules and semiconductor memory systems using the same are described herein. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input lines and the rD signal output lines in a respective point-to-point fashion.