Abstract: Horizontal dual in-line memory modules are disclosed. In one embodiment, the memory module includes a circuit board, a plurality of memory chips attached to a top surface of the circuit board, and a plurality of connector contacts disposed under a back surface of the circuit board and extending away from the memory chips, the connector contacts being electrically coupled to the memory chips, the back surface opposite the top surface of the circuit board.

Abstract: An integrated device comprising a storage location, wherein data stored in the storage location is repeatedly refreshed with a first predetermined refresh rate during a first period of time. The first period of time provides a first predetermined duration. After the end of the first period of time, the data is repeatedly refreshed with a second predetermined refresh rate.

Abstract: An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection and the memory circuit is deactivated.

Abstract: Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.

Abstract: A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.

Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.

Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, the memory device may be a package comprising a plurality of stacked memory dies.

Abstract: Horizontal dual in-line memory modules are disclosed. In one embodiment, the memory module includes a circuit board, a plurality of memory chips attached to a top surface of the circuit board, and a plurality of connector contacts disposed under a back surface of the circuit board and extending away from the memory chips, the connector contacts being electrically coupled to the memory chips, the back surface opposite the top surface of the circuit board.

Abstract: Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.

Abstract: An electronic device provides a stack of semiconductor chips. A redistribution layer of a first semiconductor chip is arranged at the bottom of the stack. The redistribution layer of the first semiconductor chip comprises external pads.

Abstract: Memory modules, computing systems, and methods of manufacturing memory modules are disclosed. In one embodiment, a memory module includes a substrate having a first side and a second side opposed to the first side. A plurality of pins is disposed on the first side of the substrate. A first plurality of memory chips are arranged in a first chip layer, the first chip layer overlying the second side of the substrate. Electrical contacts of the first plurality of memory chips are electrically coupled to the pins. A second plurality of memory chips is arranged in a second chip layer, the second chip layer overlying the first chip layer. Electrical contacts of the second plurality of memory chips are electrically coupled to the pins.

Abstract: A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.

Abstract: A memory module stores data in the form of code words, each code word comprising useful bits and check bits for error correction. The memory module contains a first group of the memory devices including check bits and a second group of the memory devices including useful bits, the second group memory devices forming ranks, each rank being addressed as a whole, the ranks forming rank groups, each rank group including at least two ranks and a first group memory device. The memory module further contains a connecting device transferring bit packets each containing useful bits and check bits in the parallel format between an interface of the memory module and the memory devices of a selected rank group.

Abstract: A semiconductor device having a stacked arrangement of a substrate and a first chip and a second chip is disclosed. In one embodiment, the first chip is arranged with a lower face on an upper face of the substrate; the second chip with a lower face on an upper face of the first chip, whereby a partial area of the upper face of the first chip that is adjacent to an edge of the first chip is uncovered by the second chip; a fifth wire contact pad is arranged on the uncovered area of the upper face of the first chip; a first bonding wire is arranged that is connected with a first wire contact pad of the substrate and the fifth wire contact pad of the first chip.

Abstract: A memory control unit for controlling a memory module comprising a plurality of memory cells, said memory control unit comprising means for detecting failure of at least one memory cell, means for deactivating said at least one defective memory cell, means for assigning the address of said at least one defective memory cell to at least one replacement memory cell, first tracking means for tracking the remaining replacement memory cells and masking means to hide the address of a defective memory cell to prevent further usage of this address instead of assigning said address to a replacement memory cell.

Abstract: An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.

Abstract: An integrated circuit includes: a terminal for outputting data, a driver for providing the data to the terminal, and a switch for selectively connecting/disconnecting the driver to the terminal. The disconnection of the driver reduces the capacitive load on the connection between the terminal and driver, thus reducing limitations on data rate from factors such as data reflections that reduce signal quality. Selective connection/disconnection allows the driver to be reconnected to the terminal only when needed.

Abstract: A chip includes a memory array and a refresh counter. The refresh counter is configured to receive refresh trigger signals. The refresh counter is configured or configurable to initiate a refresh of the memory array only once per i of the received refresh trigger signals where i is a number greater than 1.

Abstract: Embodiments of the invention relate to an integrated circuit comprising at least one functional unit configured to operate at a first clock frequency. The integrated circuit also comprises at least one first interconnect originating from a contact pad and leading to at least one frequency divider configured to receive a clock signal having a second frequency and generate one or more clock signals to operate the functional unit at the first frequency. The integrated circuit further comprises at least one second interconnect coupling an output of the frequency divider and an input of the functional unit, wherein a total length of the second wired interconnect is less than a total length of the first wired interconnects.

Abstract: A DRAM chip with a data I/O-interface of an access width equal to a page size.