Abstract: In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.

Abstract: In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.

Abstract: A non-volatile memory may include at least one cell that functions as an analog counter. In one embodiment, the counter may count the number of cycles experienced by the memory and provide an indication when a predetermined number of cycles have been completed. The completion of the given number of cycles may indicate a reliability issue.

Abstract: In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.

Abstract: In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.

Abstract: A neural network employing absolute difference calculating synapse cells comprising a pair of floating gate devices coupled in parallel between an internal cell node and column line of the network. The network further includes a switched-capacitor circuit for summing all of the charges generated by all of the synapse cells within a column of the network. The circuit operates in response to a sequence of applied voltage pulses such that each cell generates a charge representing either the input, the weight, or the minimum/maximum of either the weight or the input. The accumulation of these charges represents the sum of the absolute value difference between the input voltages and the stored weights for a single column of the array.

Abstract: A neural network providing correlation learning in a synapse cell coupled to a circuit for parallel implementation of weight adjustment provides the learning portion of the synaptic operation and includes a floating gate device having a corresponding floating gate member that stores the connection weight of the cell. Parallel weight adjustments are performed in a single operational cycle utilizing floating gate technology and control signals that facilitate programming/erasing operations.

Abstract: A neural network providing correlation learning in a synapse cell coupled to a circuit for parallel implementation of weight adjustment in a broad class of learning algorithms. The circuit provides the learning portion of the synaptic operation and includes a pair of floating gate devices sharing a common floating gate member that stores the connection weight of the cell. Parallel weight adjustments are performed in a predetermined number of cycles utilizing a novel debiasing technique.

Abstract: A semiconductor charge transfer synapse cell has a capacitor coupled between an input line and an intermediate node. A voltage pulse applied to the input line causes charge transfer from one summing line to another through a pair of series connected field-effect devices. Each of the devices has an associated gate potential which controls its resistance. In response to the low-to-high voltage transition of the input pulse current flows through the devices from the intermediate node to the summing lines. A high-to-low transition causes current to flow in the opposite direction. Because the relative conductances of the devices are different depending on the direction of current flow, a net charge is transferred from one summing line to the other. The amount of charge transferred is a function of the amplitude of the pulsed input, the gate potentials, and the capacitance value.

Abstract: A semiconductor charge domain synapse cell has a capacitor coupled between an input line and an intermediate node. A high-to-low voltage transition applied to the input line causes charge transfer from one summing line to the intermediate node through a first device having a programmable threshold. A second device then transfers the charge from the intermediate node to another summing line in response to the next low-to-high transition of the input. The amount of charge transferred is proportional the amplitude of the pulsed input, the programmed voltage threshold, and the capacitance value.

Abstract: A semiconductor charge domain synapse cell has a capacitor coupled between an input line and an intermediate node. A high-to-low voltage transition applied to the input line causes charge transfer from one summing line to the intermediate node through a first device having a programmable threshold. A second device then transfers the charge from the intermediate node to another summing line in response to the next low-to-high transition of the input. The amount of charge transferred is proportional the amplitude of the pulsed input, the programmed voltage threshold, and the capacitance value. The basic cell is shown to be extendable to two-quadrant and four-quadrant operation.

Abstract: A semiconductor charge domain synapse cell has a capacitor coupled between an input line and an intermediate node. A high-to-low voltage transition applied to the input line causes charge transfer from one summing line to the intermediate node through a first device having a programmable threshold. A second device then transfers the charge from the intermediate node to another summing line in response to the next low-to-high transition of the input. The amount of charge transferred is proportional the amplitude of the pulsed input, the programmed voltage threshold, and the capacitance value.

Abstract: Four n-channel transistor, single-stage XNOR/XOR decoding circuit provides for an improved performance of a decoding circuit using CAMs to access redundant memory.

Abstract: An analog neural network is described which provides a means for reducing the sensitivity of the network to temperature and power supply variations. A first circuit is utilized for generating a signal which exhibits a dependence on temperature corresponding to the variation normally experienced by the network in response to a change in temperature. A second circuit is employed to generate another signal which exhibits a similar dependence, except on power supply variations. By coupling these signals as inputs to the neural network the sensitivity of the network to temperature and power supply fluctuations is essentially nulified.

Abstract: An improved shield for an EPROM cell comprising a first and second metalization cover sections along with upstanding elements is disclosed. The invented shield protects selected EPROM cells from exposure to radiation in redundant memory applications. The shielding structure is designed such that radiation incident upon the memory only reaches the cell after traveling a circuitous route defined by the upstanding members. The improvement also increases the reliability of the memory while adding a degree of flexibility to the layout of the cell.

Abstract: A circuit for determining the voltage threshold of a field-effect device is described. The invention includes an amplifier means which produces an output voltage directly proportional to the current flowing within the device-under-test. A circuit means is utilized for receiving the output voltage from the amplifier means and for generating a feedback voltage at the gate of the field-effect device. This feedback voltage is dynamically limited by an RC time constant such that the feedback voltage rapidly settles to the voltage threshold of the field-effect device.

Abstract: Modified CAMs are used to generate a reset signal to other redundant CAMs which provide decoding for accessing redundant memory. Because the redundant CAMs use a single UPROM, half-latch circuit, the redundant CAMs are capable of latching to the wrong logic state. Whenever signal conditions which can cause improper latch-up are present, at least one of the modified CAMs are affected due to their sensitivity. Then, the modified CAMs will generate a reset signal until the improper latch-up condition is removed.

Abstract: The present invention covers a synapse cell for providing a weighted connection between a differential input voltage and a single output summing line having an associated capacitance. The connection is made using one or more floating-gate transistors which provide both excitatory as well as inhibitory connections. As configured, each transistor's drain is coupled to an input line and its source is coupled to the output summing line. The floating-gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a voltage pulse having a certain duration is applied to the control gate of the floating-gate transistor, a current is generated which acts to discharge the capacitance associated with the output summing line. The current is directly proportional to the charge stored on the floating-gate member and the duration of the input pulse.

Abstract: A synapse cell for providing a weighted connection between an input voltage line and an output summing line having an associated capacitance. Connection between input and output lines in the associative network is made using a dual-gate transistor. The transistor has a floating gate member for storing electrical charge, a pair of control gates coupled to a pair of input lines, and a drain coupled to an output summing line. The floating gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a binary voltage pulse having a certain duration is applied to either one or both of the control gates of the transistor, a current is generated. This current acts to discharge the capacitance associated with the output summing line. Furthermore, by employing a dual-gate structure, programming disturbance of neighboring devices in the network is practically eliminated.

Abstract: The present invention covers a synapse cell for providing a weighted connection between an input voltage line and an output summing line having an associated capacitance. Connection between input and output lines in the associative network is made using one or more floating-gate transistors which provide both excitatory as well as inhibitory connections. As configured, each transistor's control gate is coupled to an input line and its drain is coupled to an output summing line. The floating-gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a binary voltage pulse having a certain duration is applied to the control gate of the floating-gate transistor, a current is generated which acts to discharge the capacitance associated with the output summing line. The current, and therefore the resulting discharge, is directly proportional to the charge stored on the floating-gate member and the duration of the input pulse.