Patents by Inventor Hernan A. Castro

Hernan A. Castro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Operational signals generated from capacitive stored charge
    Patent number: 9711213
    Abstract: Methods, a memory device, and a system are disclosed. One such method includes applying a select pulse to a snapback device of a memory cell. This causes the memory cell to enter a conductive state. Once in the conductive state, the memory cell can be set or reset by a pulse formed from parasitic capacitive discharge from various paths coupled to the memory cell.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: July 18, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Jeremy M. Hirst, Eric S. Carman
  • MEMORY TILE ACCESS AND SELECTION PATTERNS
    Publication number: 20170192911
    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
    Type: Application
    Filed: March 20, 2017
    Publication date: July 6, 2017
    Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
  • Path isolation in a memory device
    Patent number: 9691481
    Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventor: Hernan A. Castro
  • Methods and apparatuses for modulating threshold voltages of memory cells
    Patent number: 9653127
    Abstract: Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 16, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau
  • Memory tile access and selection patterns
    Patent number: 9626292
    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: April 18, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
  • Connections for memory electrode lines
    Patent number: 9613902
    Abstract: Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: April 4, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Fabio Pellizzer, Everardo Torres Flores, Hernan A. Castro
  • PATH ISOLATION IN A MEMORY DEVICE
    Publication number: 20170069382
    Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device.
    Type: Application
    Filed: September 9, 2016
    Publication date: March 9, 2017
    Applicant: Intel Corporation
    Inventor: Hernan A. Castro
  • APPARATUSES AND METHODS FOR EFFICIENT WRITE IN A CROSS-POINT ARRAY
    Publication number: 20170047118
    Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.
    Type: Application
    Filed: August 15, 2016
    Publication date: February 16, 2017
    Inventor: Hernan Castro
  • CONNECTIONS FOR MEMORY ELECTRODE LINES
    Publication number: 20170033042
    Abstract: Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells.
    Type: Application
    Filed: August 10, 2016
    Publication date: February 2, 2017
    Inventors: Fabio Pellizzer, Everardo Torres Flores, Hernan A. Castro
  • APPARATUSES, DEVICES AND METHODS FOR SENSING A SNAPBACK EVENT IN A CIRCUIT
    Publication number: 20160365141
    Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.
    Type: Application
    Filed: June 9, 2016
    Publication date: December 15, 2016
    Inventors: Jeremy Hirst, Hernan Castro, Stephen Tang
  • INTERCONNECTION FOR MEMORY ELECTRODES
    Publication number: 20160351233
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Application
    Filed: May 27, 2016
    Publication date: December 1, 2016
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H.S. Tang
  • MEMORY TILE ACCESS AND SELECTION PATTERNS
    Publication number: 20160306740
    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 20, 2016
    Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
  • Path isolation in a memory device
    Patent number: 9466365
    Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: October 11, 2016
    Assignee: Intel Corporation
    Inventor: Hernan A. Castro
  • APPARATUSES AND METHODS FOR BI-DIRECTIONAL ACCESS OF CROSS-POINT ARRAYS
    Publication number: 20160276021
    Abstract: The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. The apparatus further comprises a memory controller configured to cause an access operation, where the access operation includes application of a first bias across a memory cell of the memory array for a selection phase of the access operation and application of a second bias, lower in magnitude than the first bias, across the memory cell for an access phase of the access operation. The memory controller is further configured to cause a direction of current flowing through the memory cell to be reversed between the selection phase and the access phase.
    Type: Application
    Filed: March 21, 2016
    Publication date: September 22, 2016
    Inventor: Hernan A. Castro
  • Connections for memory electrode lines
    Patent number: 9443562
    Abstract: Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: September 13, 2016
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Fabio Pellizzer, Everardo Torres Flores, Hernan A. Castro
  • CONNECTIONS FOR MEMORY ELECTRODE LINES
    Publication number: 20160260778
    Abstract: Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.
    Type: Application
    Filed: March 3, 2015
    Publication date: September 8, 2016
    Inventor: Hernan A. Castro
  • ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY
    Publication number: 20160240248
    Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
    Type: Application
    Filed: March 4, 2016
    Publication date: August 18, 2016
    Inventor: Hernan A. Castro
  • Apparatuses and methods for efficient write in a cross-point array
    Patent number: 9418738
    Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: August 16, 2016
    Assignee: Carlow Innovations LLC
    Inventor: Hernan Castro
  • PATH ISOLATION IN A MEMORY DEVICE
    Publication number: 20160225447
    Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device.
    Type: Application
    Filed: February 8, 2016
    Publication date: August 4, 2016
    Inventor: Hernan A. Castro
  • Memory tile access and selection patterns
    Patent number: 9406362
    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: August 2, 2016
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu